c3037774be
In preparation for switching to vmstate for migration support, fix the sizes of various GIC state fields. In particular, we replace all the bitfields (which VMState can't deal with) with straightforward uint8_t values which we do bit operations on. (The bitfields made more sense when NCPU was set differently in different situations, but we now always model at the architectural limit of 8.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1363975375-3166-3-git-send-email-peter.maydell@linaro.org
139 lines
5.1 KiB
C
139 lines
5.1 KiB
C
/*
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* ARM GIC support - internal interfaces
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_ARM_GIC_INTERNAL_H
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#define QEMU_ARM_GIC_INTERNAL_H
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#include "hw/sysbus.h"
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/* Maximum number of possible interrupts, determined by the GIC architecture */
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#define GIC_MAXIRQ 1020
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/* First 32 are private to each CPU (SGIs and PPIs). */
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#define GIC_INTERNAL 32
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/* Maximum number of possible CPU interfaces, determined by GIC architecture */
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#define NCPU 8
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#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
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/* The NVIC has 16 internal vectors. However these are not exposed
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through the normal GIC interface. */
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#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
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#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
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#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
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#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
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#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
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#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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s->priority1[irq][cpu] : \
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s->priority2[(irq) - GIC_INTERNAL])
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#define GIC_TARGET(irq) s->irq_target[irq]
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typedef struct gic_irq_state {
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/* The enable bits are only banked for per-cpu interrupts. */
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uint8_t enabled;
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uint8_t pending;
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uint8_t active;
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uint8_t level;
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bool model; /* 0 = N:N, 1 = 1:N */
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bool trigger; /* nonzero = edge triggered. */
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} gic_irq_state;
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typedef struct GICState {
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SysBusDevice busdev;
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qemu_irq parent_irq[NCPU];
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bool enabled;
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bool cpu_enabled[NCPU];
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gic_irq_state irq_state[GIC_MAXIRQ];
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uint8_t irq_target[GIC_MAXIRQ];
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uint8_t priority1[GIC_INTERNAL][NCPU];
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uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
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uint16_t last_active[GIC_MAXIRQ][NCPU];
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uint16_t priority_mask[NCPU];
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uint16_t running_irq[NCPU];
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uint16_t running_priority[NCPU];
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uint16_t current_pending[NCPU];
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uint32_t num_cpu;
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MemoryRegion iomem; /* Distributor */
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/* This is just so we can have an opaque pointer which identifies
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* both this GIC and which CPU interface we should be accessing.
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*/
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struct GICState *backref[NCPU];
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MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
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uint32_t num_irq;
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uint32_t revision;
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} GICState;
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/* The special cases for the revision property: */
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#define REV_11MPCORE 0
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#define REV_NVIC 0xffffffff
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void gic_set_pending_private(GICState *s, int cpu, int irq);
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uint32_t gic_acknowledge_irq(GICState *s, int cpu);
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void gic_complete_irq(GICState *s, int cpu, int irq);
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void gic_update(GICState *s);
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void gic_init_irqs_and_distributor(GICState *s, int num_irq);
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#define TYPE_ARM_GIC_COMMON "arm_gic_common"
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#define ARM_GIC_COMMON(obj) \
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OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
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#define ARM_GIC_COMMON_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
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#define ARM_GIC_COMMON_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
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typedef struct ARMGICCommonClass {
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SysBusDeviceClass parent_class;
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void (*pre_save)(GICState *s);
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void (*post_load)(GICState *s);
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} ARMGICCommonClass;
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#define TYPE_ARM_GIC "arm_gic"
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#define ARM_GIC(obj) \
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OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
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#define ARM_GIC_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC)
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#define ARM_GIC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
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typedef struct ARMGICClass {
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ARMGICCommonClass parent_class;
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DeviceRealize parent_realize;
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} ARMGICClass;
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#endif /* !QEMU_ARM_GIC_INTERNAL_H */
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