130 lines
5.5 KiB
Plaintext
130 lines
5.5 KiB
Plaintext
#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# Fields:
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%rd 7:5
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%rs1_3 7:3 !function=ex_rvc_register
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%rs2_3 2:3 !function=ex_rvc_register
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%rs2_5 2:5
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# Immediates:
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%imm_ci 12:s1 2:5
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%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
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%uimm_cl_d 5:2 10:3 !function=ex_shift_3
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%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
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%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
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%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
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%nzuimm_6bit 12:1 2:5
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%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
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%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
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%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
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%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
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%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
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%imm_lui 12:s1 2:5 !function=ex_shift_12
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# Argument sets:
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&cl rs1 rd
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&cl_dw uimm rs1 rd
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&ci imm rd
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&ciw nzuimm rd
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&cs rs1 rs2
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&cs_dw uimm rs1 rs2
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&cb imm rs1
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&cr rd rs2
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&cj imm
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&c_shift shamt rd
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&c_ld uimm rd
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&c_sd uimm rs2
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&caddi16sp_lui imm_lui imm_addi16sp rd
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&cflwsp_ldsp uimm_flwsp uimm_ldsp rd
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&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2
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# Formats 16:
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@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
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@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
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@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
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@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
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@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
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@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
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@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
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@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
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@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
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@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
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@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
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@cj ... ........... .. &cj imm=%imm_cj
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@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
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@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
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@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
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@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
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@c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
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@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
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uimm_ldsp=%uimm_6bit_ld %rd
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@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
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uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
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@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
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@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
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@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
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# *** RV64C Standard Extension (Quadrant 0) ***
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c_addi4spn 000 ........ ... 00 @ciw
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c_fld 001 ... ... .. ... 00 @cl_d
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c_lw 010 ... ... .. ... 00 @cl_w
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c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
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c_fsd 101 ... ... .. ... 00 @cs_d
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c_sw 110 ... ... .. ... 00 @cs_w
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c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
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# *** RV64C Standard Extension (Quadrant 1) ***
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c_addi 000 . ..... ..... 01 @ci
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c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
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c_li 010 . ..... ..... 01 @ci
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c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
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c_srli 100 . 00 ... ..... 01 @c_shift
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c_srai 100 . 01 ... ..... 01 @c_shift
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c_andi 100 . 10 ... ..... 01 @c_andi
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c_sub 100 0 11 ... 00 ... 01 @cs_2
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c_xor 100 0 11 ... 01 ... 01 @cs_2
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c_or 100 0 11 ... 10 ... 01 @cs_2
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c_and 100 0 11 ... 11 ... 01 @cs_2
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c_subw 100 1 11 ... 00 ... 01 @cs_2
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c_addw 100 1 11 ... 01 ... 01 @cs_2
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c_j 101 ........... 01 @cj
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c_beqz 110 ... ... ..... 01 @cb
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c_bnez 111 ... ... ..... 01 @cb
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# *** RV64C Standard Extension (Quadrant 2) ***
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c_slli 000 . ..... ..... 10 @c_shift2
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c_fldsp 001 . ..... ..... 10 @c_ld
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c_lwsp 010 . ..... ..... 10 @c_lw
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c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
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c_jr_mv 100 0 ..... ..... 10 @cr
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c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
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c_fsdsp 101 ...... ..... 10 @c_sd
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c_swsp 110 . ..... ..... 10 @c_sw
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c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
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