0d09e41a51
Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
128 lines
3.8 KiB
C
128 lines
3.8 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on acpi.c, but heavily rewritten.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*
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*/
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/i2c/pm_smbus.h"
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#include "hw/pci/pci.h"
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#include "sysemu/sysemu.h"
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#include "hw/i2c/i2c.h"
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#include "hw/i2c/smbus.h"
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#include "hw/i386/ich9.h"
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#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
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#define ICH9_SMB_DEVICE(obj) \
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OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
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typedef struct ICH9SMBState {
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PCIDevice dev;
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PMSMBus smb;
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} ICH9SMBState;
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static const VMStateDescription vmstate_ich9_smbus = {
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.name = "ich9_smb",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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ICH9SMBState *s = ICH9_SMB_DEVICE(d);
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pci_default_write_config(d, address, val, len);
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if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
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uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
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if ((hostc & ICH9_SMB_HOSTC_HST_EN) &&
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!(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
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memory_region_set_enabled(&s->smb.io, true);
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} else {
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memory_region_set_enabled(&s->smb.io, false);
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}
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}
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}
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static int ich9_smbus_initfn(PCIDevice *d)
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{
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ICH9SMBState *s = ICH9_SMB_DEVICE(d);
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/* TODO? D31IP.SMIP in chipset configuration space */
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pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
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pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
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/* TODO bar0, bar1: 64bit BAR support*/
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pm_smbus_init(&d->qdev, &s->smb);
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pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
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&s->smb.io);
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return 0;
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}
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static void ich9_smb_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
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k->revision = ICH9_A2_SMB_REVISION;
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k->class_id = PCI_CLASS_SERIAL_SMBUS;
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dc->no_user = 1;
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dc->vmsd = &vmstate_ich9_smbus;
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dc->desc = "ICH9 SMBUS Bridge";
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k->init = ich9_smbus_initfn;
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k->config_write = ich9_smbus_write_config;
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}
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i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
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{
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PCIDevice *d =
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pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
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ICH9SMBState *s = ICH9_SMB_DEVICE(d);
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return s->smb.smbus;
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}
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static const TypeInfo ich9_smb_info = {
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.name = TYPE_ICH9_SMB_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(ICH9SMBState),
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.class_init = ich9_smb_class_init,
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};
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static void ich9_smb_register(void)
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{
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type_register_static(&ich9_smb_info);
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}
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type_init(ich9_smb_register);
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