204 lines
5.9 KiB
C
204 lines
5.9 KiB
C
#ifndef CPU_SPARC_H
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#define CPU_SPARC_H
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#include "config.h"
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#if !defined(TARGET_SPARC64)
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#define TARGET_LONG_BITS 32
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#define TARGET_FPREGS 32
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#define TARGET_FPREG_T float
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#else
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#define TARGET_LONG_BITS 64
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#define TARGET_FPREGS 64
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#define TARGET_FPREG_T double
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#endif
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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/*#define EXCP_INTERRUPT 0x100*/
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/* trap definitions */
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#define TT_TFAULT 0x01
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#define TT_ILL_INSN 0x02
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#define TT_PRIV_INSN 0x03
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#define TT_NFPU_INSN 0x04
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#define TT_WIN_OVF 0x05
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#define TT_WIN_UNF 0x06
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#define TT_FP_EXCP 0x08
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#define TT_DFAULT 0x09
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#define TT_EXTINT 0x10
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#define TT_DIV_ZERO 0x2a
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#define TT_TRAP 0x80
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#define PSR_NEG (1<<23)
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#define PSR_ZERO (1<<22)
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#define PSR_OVF (1<<21)
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#define PSR_CARRY (1<<20)
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#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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#define PSR_EF (1<<12)
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#define PSR_PIL 0xf00
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#define PSR_S (1<<7)
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#define PSR_PS (1<<6)
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#define PSR_ET (1<<5)
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#define PSR_CWP 0x1f
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/* Trap base register */
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#define TBR_BASE_MASK 0xfffff000
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/* Fcc */
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#define FSR_RD1 (1<<31)
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#define FSR_RD0 (1<<30)
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#define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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#define FSR_RD_NEAREST 0
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#define FSR_RD_ZERO FSR_RD0
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#define FSR_RD_POS FSR_RD1
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#define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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#define FSR_NVM (1<<27)
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#define FSR_OFM (1<<26)
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#define FSR_UFM (1<<25)
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#define FSR_DZM (1<<24)
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#define FSR_NXM (1<<23)
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#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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#define FSR_NVA (1<<9)
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#define FSR_OFA (1<<8)
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#define FSR_UFA (1<<7)
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#define FSR_DZA (1<<6)
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#define FSR_NXA (1<<5)
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#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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#define FSR_NVC (1<<4)
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#define FSR_OFC (1<<3)
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#define FSR_UFC (1<<2)
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#define FSR_DZC (1<<1)
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#define FSR_NXC (1<<0)
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#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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#define FSR_FTT2 (1<<16)
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#define FSR_FTT1 (1<<15)
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#define FSR_FTT0 (1<<14)
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#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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#define FSR_FTT_IEEE_EXCP (1 << 14)
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#define FSR_FTT_UNIMPFPOP (3 << 14)
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#define FSR_FTT_INVAL_FPR (6 << 14)
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#define FSR_FCC1 (1<<11)
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#define FSR_FCC0 (1<<10)
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/* MMU */
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#define MMU_E (1<<0)
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#define MMU_NF (1<<1)
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#define PTE_ENTRYTYPE_MASK 3
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#define PTE_ACCESS_MASK 0x1c
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#define PTE_ACCESS_SHIFT 2
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#define PTE_PPN_SHIFT 7
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#define PTE_ADDR_MASK 0xffffff00
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#define PG_ACCESSED_BIT 5
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#define PG_MODIFIED_BIT 6
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#define PG_CACHE_BIT 7
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
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#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
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/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
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#define NWINDOWS 8
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typedef struct CPUSPARCState {
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target_ulong gregs[8]; /* general registers */
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target_ulong *regwptr; /* pointer to current register window */
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TARGET_FPREG_T fpr[TARGET_FPREGS]; /* floating point registers */
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target_ulong pc; /* program counter */
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target_ulong npc; /* next program counter */
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target_ulong y; /* multiply/divide register */
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uint32_t psr; /* processor state register */
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uint32_t fsr; /* FPU state register */
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uint32_t cwp; /* index of current register window (extracted
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from PSR) */
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uint32_t wim; /* window invalid mask */
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uint32_t tbr; /* trap base register */
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int psrs; /* supervisor mode (extracted from PSR) */
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int psrps; /* previous supervisor mode */
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int psret; /* enable traps */
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int psrpil; /* interrupt level */
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int psref; /* enable fpu */
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jmp_buf jmp_env;
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int user_mode_only;
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int exception_index;
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int interrupt_index;
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int interrupt_request;
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struct TranslationBlock *current_tb;
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void *opaque;
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/* NOTE: we allow 8 more registers to handle wrapping */
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target_ulong regbase[NWINDOWS * 16 + 8];
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/* in order to avoid passing too many arguments to the memory
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write helpers, we store some rarely used information in the CPU
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context) */
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unsigned long mem_write_pc; /* host pc at which the memory was
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written */
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unsigned long mem_write_vaddr; /* target virtual addr at which the
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memory was written */
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/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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/* MMU regs */
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uint32_t mmuregs[16];
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/* temporary float registers */
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float ft0, ft1, ft2;
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double dt0, dt1, dt2;
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float_status fp_status;
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#if defined(TARGET_SPARC64)
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target_ulong t0, t1, t2;
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#endif
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/* ice debug support */
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target_ulong breakpoints[MAX_BREAKPOINTS];
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int nb_breakpoints;
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int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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} CPUSPARCState;
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CPUSPARCState *cpu_sparc_init(void);
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int cpu_sparc_exec(CPUSPARCState *s);
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int cpu_sparc_close(CPUSPARCState *s);
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void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f);
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double cpu_put_fp64(uint64_t mant, uint16_t exp);
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/* Fake impl 0, version 4 */
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#define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \
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(env->psref? PSR_EF : 0) | \
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(env->psrpil << 8) | \
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(env->psrs? PSR_S : 0) | \
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(env->psrps? PSR_PS : 0) | \
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(env->psret? PSR_ET : 0) | env->cwp)
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#ifndef NO_CPU_IO_DEFS
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void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
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#endif
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#define PUT_PSR(env, val) do { int _tmp = val; \
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env->psr = _tmp & PSR_ICC; \
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env->psref = (_tmp & PSR_EF)? 1 : 0; \
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env->psrpil = (_tmp & PSR_PIL) >> 8; \
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env->psrs = (_tmp & PSR_S)? 1 : 0; \
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env->psrps = (_tmp & PSR_PS)? 1 : 0; \
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env->psret = (_tmp & PSR_ET)? 1 : 0; \
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cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
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} while (0)
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struct siginfo;
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int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
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#define TARGET_PAGE_BITS 12 /* 4k */
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#include "cpu-all.h"
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#endif
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