728 lines
20 KiB
C
728 lines
20 KiB
C
/*
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* Test Server
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*
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* Copyright IBM, Corp. 2011
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "sysemu/qtest.h"
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#include "hw/qdev.h"
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#include "sysemu/char.h"
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#include "exec/ioport.h"
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#include "exec/memory.h"
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#include "hw/irq.h"
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#include "sysemu/accel.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/cpus.h"
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#include "qemu/config-file.h"
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#include "qemu/option.h"
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#include "qemu/error-report.h"
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#include "qemu/cutils.h"
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#ifdef TARGET_PPC64
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#include "hw/ppc/spapr_rtas.h"
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#endif
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#define MAX_IRQ 256
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bool qtest_allowed;
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static DeviceState *irq_intercept_dev;
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static FILE *qtest_log_fp;
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static CharBackend qtest_chr;
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static GString *inbuf;
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static int irq_levels[MAX_IRQ];
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static qemu_timeval start_time;
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static bool qtest_opened;
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#define FMT_timeval "%ld.%06ld"
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/**
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* QTest Protocol
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*
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* Line based protocol, request/response based. Server can send async messages
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* so clients should always handle many async messages before the response
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* comes in.
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*
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* Valid requests
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*
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* Clock management:
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*
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* The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
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* let you adjust the value of the clock (monotonically). All the commands
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* return the current value of the clock in nanoseconds.
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*
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* > clock_step
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* < OK VALUE
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*
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* Advance the clock to the next deadline. Useful when waiting for
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* asynchronous events.
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*
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* > clock_step NS
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* < OK VALUE
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*
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* Advance the clock by NS nanoseconds.
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*
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* > clock_set NS
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* < OK VALUE
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*
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* Advance the clock to NS nanoseconds (do nothing if it's already past).
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*
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* PIO and memory access:
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*
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* > outb ADDR VALUE
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* < OK
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*
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* > outw ADDR VALUE
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* < OK
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*
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* > outl ADDR VALUE
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* < OK
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*
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* > inb ADDR
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* < OK VALUE
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*
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* > inw ADDR
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* < OK VALUE
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*
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* > inl ADDR
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* < OK VALUE
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*
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* > writeb ADDR VALUE
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* < OK
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*
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* > writew ADDR VALUE
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* < OK
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*
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* > writel ADDR VALUE
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* < OK
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*
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* > writeq ADDR VALUE
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* < OK
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*
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* > readb ADDR
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* < OK VALUE
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*
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* > readw ADDR
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* < OK VALUE
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*
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* > readl ADDR
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* < OK VALUE
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*
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* > readq ADDR
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* < OK VALUE
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*
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* > read ADDR SIZE
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* < OK DATA
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*
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* > write ADDR SIZE DATA
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* < OK
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*
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* > b64read ADDR SIZE
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* < OK B64_DATA
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*
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* > b64write ADDR SIZE B64_DATA
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* < OK
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*
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* > memset ADDR SIZE VALUE
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* < OK
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*
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* ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
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* For 'memset' a zero size is permitted and does nothing.
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*
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* DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
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* than the expected size, the value will be zero filled at the end of the data
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* sequence.
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*
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* B64_DATA is an arbitrarily long base64 encoded string.
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* If the sizes do not match, the data will be truncated.
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*
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* IRQ management:
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*
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* > irq_intercept_in QOM-PATH
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* < OK
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*
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* > irq_intercept_out QOM-PATH
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* < OK
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*
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* Attach to the gpio-in (resp. gpio-out) pins exported by the device at
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* QOM-PATH. When the pin is triggered, one of the following async messages
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* will be printed to the qtest stream:
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*
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* IRQ raise NUM
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* IRQ lower NUM
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*
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* where NUM is an IRQ number. For the PC, interrupts can be intercepted
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* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
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* NUM=0 even though it is remapped to GSI 2).
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*/
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static int hex2nib(char ch)
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{
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if (ch >= '0' && ch <= '9') {
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return ch - '0';
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} else if (ch >= 'a' && ch <= 'f') {
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return 10 + (ch - 'a');
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} else if (ch >= 'A' && ch <= 'F') {
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return 10 + (ch - 'A');
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} else {
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return -1;
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}
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}
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static void qtest_get_time(qemu_timeval *tv)
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{
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qemu_gettimeofday(tv);
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tv->tv_sec -= start_time.tv_sec;
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tv->tv_usec -= start_time.tv_usec;
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if (tv->tv_usec < 0) {
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tv->tv_usec += 1000000;
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tv->tv_sec -= 1;
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}
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}
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static void qtest_send_prefix(CharBackend *chr)
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{
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qemu_timeval tv;
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if (!qtest_log_fp || !qtest_opened) {
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return;
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}
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qtest_get_time(&tv);
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fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
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(long) tv.tv_sec, (long) tv.tv_usec);
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}
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static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
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{
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va_list ap;
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if (!qtest_log_fp || !qtest_opened) {
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return;
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}
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qtest_send_prefix(NULL);
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va_start(ap, fmt);
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vfprintf(qtest_log_fp, fmt, ap);
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va_end(ap);
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}
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static void do_qtest_send(CharBackend *chr, const char *str, size_t len)
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{
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qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
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if (qtest_log_fp && qtest_opened) {
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fprintf(qtest_log_fp, "%s", str);
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}
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}
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static void qtest_send(CharBackend *chr, const char *str)
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{
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do_qtest_send(chr, str, strlen(str));
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}
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static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr,
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const char *fmt, ...)
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{
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va_list ap;
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gchar *buffer;
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va_start(ap, fmt);
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buffer = g_strdup_vprintf(fmt, ap);
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qtest_send(chr, buffer);
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g_free(buffer);
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va_end(ap);
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}
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static void qtest_irq_handler(void *opaque, int n, int level)
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{
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qemu_irq old_irq = *(qemu_irq *)opaque;
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qemu_set_irq(old_irq, level);
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if (irq_levels[n] != level) {
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CharBackend *chr = &qtest_chr;
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irq_levels[n] = level;
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qtest_send_prefix(chr);
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qtest_sendf(chr, "IRQ %s %d\n",
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level ? "raise" : "lower", n);
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}
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}
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static void qtest_process_command(CharBackend *chr, gchar **words)
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{
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const gchar *command;
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g_assert(words);
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command = words[0];
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if (qtest_log_fp) {
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qemu_timeval tv;
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int i;
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qtest_get_time(&tv);
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fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
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(long) tv.tv_sec, (long) tv.tv_usec);
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for (i = 0; words[i]; i++) {
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fprintf(qtest_log_fp, " %s", words[i]);
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}
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fprintf(qtest_log_fp, "\n");
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}
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g_assert(command);
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if (strcmp(words[0], "irq_intercept_out") == 0
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|| strcmp(words[0], "irq_intercept_in") == 0) {
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DeviceState *dev;
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NamedGPIOList *ngl;
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g_assert(words[1]);
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dev = DEVICE(object_resolve_path(words[1], NULL));
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if (!dev) {
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qtest_send_prefix(chr);
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qtest_send(chr, "FAIL Unknown device\n");
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return;
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}
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if (irq_intercept_dev) {
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qtest_send_prefix(chr);
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if (irq_intercept_dev != dev) {
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qtest_send(chr, "FAIL IRQ intercept already enabled\n");
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} else {
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qtest_send(chr, "OK\n");
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}
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return;
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}
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QLIST_FOREACH(ngl, &dev->gpios, node) {
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/* We don't support intercept of named GPIOs yet */
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if (ngl->name) {
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continue;
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}
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if (words[0][14] == 'o') {
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int i;
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for (i = 0; i < ngl->num_out; ++i) {
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qemu_irq *disconnected = g_new0(qemu_irq, 1);
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qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
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disconnected, i);
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*disconnected = qdev_intercept_gpio_out(dev, icpt,
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ngl->name, i);
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}
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} else {
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qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
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ngl->num_in);
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}
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}
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irq_intercept_dev = dev;
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qtest_send_prefix(chr);
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qtest_send(chr, "OK\n");
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} else if (strcmp(words[0], "outb") == 0 ||
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strcmp(words[0], "outw") == 0 ||
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strcmp(words[0], "outl") == 0) {
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unsigned long addr;
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unsigned long value;
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g_assert(words[1] && words[2]);
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g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
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g_assert(qemu_strtoul(words[2], NULL, 0, &value) == 0);
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g_assert(addr <= 0xffff);
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if (words[0][3] == 'b') {
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cpu_outb(addr, value);
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} else if (words[0][3] == 'w') {
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cpu_outw(addr, value);
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} else if (words[0][3] == 'l') {
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cpu_outl(addr, value);
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}
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qtest_send_prefix(chr);
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qtest_send(chr, "OK\n");
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} else if (strcmp(words[0], "inb") == 0 ||
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strcmp(words[0], "inw") == 0 ||
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strcmp(words[0], "inl") == 0) {
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unsigned long addr;
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uint32_t value = -1U;
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g_assert(words[1]);
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g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
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g_assert(addr <= 0xffff);
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if (words[0][2] == 'b') {
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value = cpu_inb(addr);
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} else if (words[0][2] == 'w') {
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value = cpu_inw(addr);
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} else if (words[0][2] == 'l') {
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value = cpu_inl(addr);
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}
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qtest_send_prefix(chr);
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qtest_sendf(chr, "OK 0x%04x\n", value);
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} else if (strcmp(words[0], "writeb") == 0 ||
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strcmp(words[0], "writew") == 0 ||
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strcmp(words[0], "writel") == 0 ||
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strcmp(words[0], "writeq") == 0) {
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uint64_t addr;
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uint64_t value;
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g_assert(words[1] && words[2]);
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g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
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g_assert(qemu_strtou64(words[2], NULL, 0, &value) == 0);
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if (words[0][5] == 'b') {
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uint8_t data = value;
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cpu_physical_memory_write(addr, &data, 1);
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} else if (words[0][5] == 'w') {
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uint16_t data = value;
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tswap16s(&data);
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cpu_physical_memory_write(addr, &data, 2);
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} else if (words[0][5] == 'l') {
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uint32_t data = value;
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tswap32s(&data);
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cpu_physical_memory_write(addr, &data, 4);
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} else if (words[0][5] == 'q') {
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uint64_t data = value;
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tswap64s(&data);
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cpu_physical_memory_write(addr, &data, 8);
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}
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qtest_send_prefix(chr);
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qtest_send(chr, "OK\n");
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} else if (strcmp(words[0], "readb") == 0 ||
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strcmp(words[0], "readw") == 0 ||
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strcmp(words[0], "readl") == 0 ||
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strcmp(words[0], "readq") == 0) {
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uint64_t addr;
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uint64_t value = UINT64_C(-1);
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g_assert(words[1]);
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g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
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if (words[0][4] == 'b') {
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uint8_t data;
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cpu_physical_memory_read(addr, &data, 1);
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value = data;
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} else if (words[0][4] == 'w') {
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uint16_t data;
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cpu_physical_memory_read(addr, &data, 2);
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value = tswap16(data);
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} else if (words[0][4] == 'l') {
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uint32_t data;
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cpu_physical_memory_read(addr, &data, 4);
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value = tswap32(data);
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} else if (words[0][4] == 'q') {
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cpu_physical_memory_read(addr, &value, 8);
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tswap64s(&value);
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}
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qtest_send_prefix(chr);
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qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
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} else if (strcmp(words[0], "read") == 0) {
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uint64_t addr, len, i;
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uint8_t *data;
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char *enc;
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g_assert(words[1] && words[2]);
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g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
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g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
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/* We'd send garbage to libqtest if len is 0 */
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g_assert(len);
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data = g_malloc(len);
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cpu_physical_memory_read(addr, data, len);
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enc = g_malloc(2 * len + 1);
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for (i = 0; i < len; i++) {
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sprintf(&enc[i * 2], "%02x", data[i]);
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}
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qtest_send_prefix(chr);
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qtest_sendf(chr, "OK 0x%s\n", enc);
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g_free(data);
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g_free(enc);
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} else if (strcmp(words[0], "b64read") == 0) {
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uint64_t addr, len;
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uint8_t *data;
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gchar *b64_data;
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g_assert(words[1] && words[2]);
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g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
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g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
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data = g_malloc(len);
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cpu_physical_memory_read(addr, data, len);
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b64_data = g_base64_encode(data, len);
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qtest_send_prefix(chr);
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qtest_sendf(chr, "OK %s\n", b64_data);
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g_free(data);
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g_free(b64_data);
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} else if (strcmp(words[0], "write") == 0) {
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uint64_t addr, len, i;
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uint8_t *data;
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size_t data_len;
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g_assert(words[1] && words[2] && words[3]);
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g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
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g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
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data_len = strlen(words[3]);
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if (data_len < 3) {
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qtest_send(chr, "ERR invalid argument size\n");
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return;
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}
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data = g_malloc(len);
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for (i = 0; i < len; i++) {
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if ((i * 2 + 4) <= data_len) {
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data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
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data[i] |= hex2nib(words[3][i * 2 + 3]);
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} else {
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data[i] = 0;
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}
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}
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cpu_physical_memory_write(addr, data, len);
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g_free(data);
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qtest_send_prefix(chr);
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qtest_send(chr, "OK\n");
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} else if (strcmp(words[0], "memset") == 0) {
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uint64_t addr, len;
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uint8_t *data;
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unsigned long pattern;
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g_assert(words[1] && words[2] && words[3]);
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g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
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g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
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g_assert(qemu_strtoul(words[3], NULL, 0, &pattern) == 0);
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if (len) {
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data = g_malloc(len);
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memset(data, pattern, len);
|
|
cpu_physical_memory_write(addr, data, len);
|
|
g_free(data);
|
|
}
|
|
|
|
qtest_send_prefix(chr);
|
|
qtest_send(chr, "OK\n");
|
|
} else if (strcmp(words[0], "b64write") == 0) {
|
|
uint64_t addr, len;
|
|
uint8_t *data;
|
|
size_t data_len;
|
|
gsize out_len;
|
|
|
|
g_assert(words[1] && words[2] && words[3]);
|
|
g_assert(qemu_strtou64(words[1], NULL, 0, &addr) == 0);
|
|
g_assert(qemu_strtou64(words[2], NULL, 0, &len) == 0);
|
|
|
|
data_len = strlen(words[3]);
|
|
if (data_len < 3) {
|
|
qtest_send(chr, "ERR invalid argument size\n");
|
|
return;
|
|
}
|
|
|
|
data = g_base64_decode_inplace(words[3], &out_len);
|
|
if (out_len != len) {
|
|
qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
|
|
"found %zu)\n",
|
|
len, out_len);
|
|
out_len = MIN(out_len, len);
|
|
}
|
|
|
|
cpu_physical_memory_write(addr, data, out_len);
|
|
|
|
qtest_send_prefix(chr);
|
|
qtest_send(chr, "OK\n");
|
|
} else if (strcmp(words[0], "endianness") == 0) {
|
|
qtest_send_prefix(chr);
|
|
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
qtest_sendf(chr, "OK big\n");
|
|
#else
|
|
qtest_sendf(chr, "OK little\n");
|
|
#endif
|
|
#ifdef TARGET_PPC64
|
|
} else if (strcmp(words[0], "rtas") == 0) {
|
|
uint64_t res, args, ret;
|
|
unsigned long nargs, nret;
|
|
|
|
g_assert(qemu_strtoul(words[2], NULL, 0, &nargs) == 0);
|
|
g_assert(qemu_strtou64(words[3], NULL, 0, &args) == 0);
|
|
g_assert(qemu_strtoul(words[4], NULL, 0, &nret) == 0);
|
|
g_assert(qemu_strtou64(words[5], NULL, 0, &ret) == 0);
|
|
res = qtest_rtas_call(words[1], nargs, args, nret, ret);
|
|
|
|
qtest_send_prefix(chr);
|
|
qtest_sendf(chr, "OK %"PRIu64"\n", res);
|
|
#endif
|
|
} else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
|
|
int64_t ns;
|
|
|
|
if (words[1]) {
|
|
g_assert(qemu_strtoi64(words[1], NULL, 0, &ns) == 0);
|
|
} else {
|
|
ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
|
|
}
|
|
qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
|
|
qtest_send_prefix(chr);
|
|
qtest_sendf(chr, "OK %"PRIi64"\n",
|
|
(int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
|
} else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
|
|
int64_t ns;
|
|
|
|
g_assert(words[1]);
|
|
g_assert(qemu_strtoi64(words[1], NULL, 0, &ns) == 0);
|
|
qtest_clock_warp(ns);
|
|
qtest_send_prefix(chr);
|
|
qtest_sendf(chr, "OK %"PRIi64"\n",
|
|
(int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
|
} else {
|
|
qtest_send_prefix(chr);
|
|
qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
|
|
}
|
|
}
|
|
|
|
static void qtest_process_inbuf(CharBackend *chr, GString *inbuf)
|
|
{
|
|
char *end;
|
|
|
|
while ((end = strchr(inbuf->str, '\n')) != NULL) {
|
|
size_t offset;
|
|
GString *cmd;
|
|
gchar **words;
|
|
|
|
offset = end - inbuf->str;
|
|
|
|
cmd = g_string_new_len(inbuf->str, offset);
|
|
g_string_erase(inbuf, 0, offset + 1);
|
|
|
|
words = g_strsplit(cmd->str, " ", 0);
|
|
qtest_process_command(chr, words);
|
|
g_strfreev(words);
|
|
|
|
g_string_free(cmd, TRUE);
|
|
}
|
|
}
|
|
|
|
static void qtest_read(void *opaque, const uint8_t *buf, int size)
|
|
{
|
|
CharBackend *chr = opaque;
|
|
|
|
g_string_append_len(inbuf, (const gchar *)buf, size);
|
|
qtest_process_inbuf(chr, inbuf);
|
|
}
|
|
|
|
static int qtest_can_read(void *opaque)
|
|
{
|
|
return 1024;
|
|
}
|
|
|
|
static void qtest_event(void *opaque, int event)
|
|
{
|
|
int i;
|
|
|
|
switch (event) {
|
|
case CHR_EVENT_OPENED:
|
|
/*
|
|
* We used to call qemu_system_reset() here, hoping we could
|
|
* use the same process for multiple tests that way. Never
|
|
* used. Injects an extra reset even when it's not used, and
|
|
* that can mess up tests, e.g. -boot once.
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
|
|
irq_levels[i] = 0;
|
|
}
|
|
qemu_gettimeofday(&start_time);
|
|
qtest_opened = true;
|
|
if (qtest_log_fp) {
|
|
fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
|
|
(long) start_time.tv_sec, (long) start_time.tv_usec);
|
|
}
|
|
break;
|
|
case CHR_EVENT_CLOSED:
|
|
qtest_opened = false;
|
|
if (qtest_log_fp) {
|
|
qemu_timeval tv;
|
|
qtest_get_time(&tv);
|
|
fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
|
|
(long) tv.tv_sec, (long) tv.tv_usec);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int qtest_init_accel(MachineState *ms)
|
|
{
|
|
QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
|
|
&error_abort);
|
|
qemu_opt_set(opts, "shift", "0", &error_abort);
|
|
configure_icount(opts, &error_abort);
|
|
qemu_opts_del(opts);
|
|
return 0;
|
|
}
|
|
|
|
void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
|
|
{
|
|
Chardev *chr;
|
|
|
|
chr = qemu_chr_new("qtest", qtest_chrdev);
|
|
|
|
if (chr == NULL) {
|
|
error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
|
|
qtest_chrdev);
|
|
return;
|
|
}
|
|
|
|
if (qtest_log) {
|
|
if (strcmp(qtest_log, "none") != 0) {
|
|
qtest_log_fp = fopen(qtest_log, "w+");
|
|
}
|
|
} else {
|
|
qtest_log_fp = stderr;
|
|
}
|
|
|
|
qemu_chr_fe_init(&qtest_chr, chr, errp);
|
|
qemu_chr_fe_set_handlers(&qtest_chr, qtest_can_read, qtest_read,
|
|
qtest_event, &qtest_chr, NULL, true);
|
|
qemu_chr_fe_set_echo(&qtest_chr, true);
|
|
|
|
inbuf = g_string_new("");
|
|
}
|
|
|
|
bool qtest_driver(void)
|
|
{
|
|
return qtest_chr.chr != NULL;
|
|
}
|
|
|
|
static void qtest_accel_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AccelClass *ac = ACCEL_CLASS(oc);
|
|
ac->name = "QTest";
|
|
ac->available = qtest_available;
|
|
ac->init_machine = qtest_init_accel;
|
|
ac->allowed = &qtest_allowed;
|
|
}
|
|
|
|
#define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
|
|
|
|
static const TypeInfo qtest_accel_type = {
|
|
.name = TYPE_QTEST_ACCEL,
|
|
.parent = TYPE_ACCEL,
|
|
.class_init = qtest_accel_class_init,
|
|
};
|
|
|
|
static void qtest_type_init(void)
|
|
{
|
|
type_register_static(&qtest_accel_type);
|
|
}
|
|
|
|
type_init(qtest_type_init);
|