qemu-e2k/include
Peter Maydell 20b8016ed8 First RISC-V PR for 6.0
This PR:
  - Fixes some issues with the m25p80
  - Improves GDB support for RISC-V
  - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
  - Enforces PMP exceptions correctly
  - Fixes some Coverity issues
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210117-3' into staging

First RISC-V PR for 6.0

This PR:
 - Fixes some issues with the m25p80
 - Improves GDB support for RISC-V
 - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
 - Enforces PMP exceptions correctly
 - Fixes some Coverity issues

# gpg: Signature made Sun 17 Jan 2021 21:53:19 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210117-3:
  riscv: Pass RISCVHartArrayState by pointer
  target/riscv: Remove built-in GDB XML files for CSRs
  target/riscv: Generate the GDB XML file for CSR registers dynamically
  target/riscv: Add CSR name in the CSR function table
  target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
  hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
  hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
  target/riscv/pmp: Raise exception if no PMP entry is configured
  RISC-V: Place DTB at 3GB boundary instead of 4GB
  gdb: riscv: Add target description
  hw/block: m25p80: Implement AAI-WP command support for SST flashes
  hw/block: m25p80: Don't write to flash if write is disabled

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18 10:28:26 +00:00
..
authz authz: Fix Lesser GPL version number 2020-10-29 09:57:37 +00:00
block block: introduce BDRV_REQ_NO_WAIT flag 2020-12-18 12:35:55 +01:00
chardev chardev: do not use machine_init_done 2020-12-15 12:51:51 -05:00
crypto
disas disas: Push const down through host disassembly 2021-01-07 05:09:42 -10:00
exec tcg: Use tcg_constant_i32 with icount expander 2021-01-13 08:39:08 -10:00
fpu
hw First RISC-V PR for 6.0 2021-01-18 10:28:26 +00:00
io io: Document qmp oob suitability of qio_channel_shutdown and io_shutdown 2021-01-13 10:21:17 +01:00
libdecnumber
migration migration: Replace migration's JSON writer by the general one 2020-12-19 10:39:16 +01:00
monitor sev: add sev-inject-launch-secret 2020-12-10 17:33:17 -05:00
net qdev: Move softmmu properties to qdev-properties-system.h 2020-12-18 15:20:17 -05:00
qapi qobject: Make QString immutable 2020-12-19 10:39:41 +01:00
qemu Introduce yank feature 2021-01-13 10:21:17 +01:00
qom
scsi
standard-headers target/i386: Support up to 32768 CPUs without IRQ remapping 2020-12-10 12:15:00 -05:00
sysemu whpx: move internal definitions to whpx-internal.h 2021-01-12 12:38:03 +01:00
tcg tcg: Remove tcg_gen_dup{8,16,32,64}i_vec 2021-01-13 08:39:08 -10:00
ui ui/gtk: expose gd_monitor_update_interval 2021-01-15 11:22:42 +01:00
user
elf.h target-arm queue: 2020-10-29 11:40:04 +00:00
glib-compat.h glib-compat: add g_unix_get_passwd_entry_qemu() 2020-11-02 19:52:08 -06:00
qemu-common.h vl: extract softmmu/datadir.c 2020-12-10 12:15:18 -05:00
qemu-io.h
trace-tcg.h