Richard Henderson 20dc52a37c target/openrisc: Enable trap, csync, msync, psync for user mode ... Not documented as disabled for user mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>		2017-02-14 08:15:00 +11:00
..
cpu.c	target/openrisc: Implement lwa, swa	2017-02-14 08:14:59 +11:00
cpu.h	target/openrisc: Keep SR_CY and SR_OV in a separate variables	2017-02-14 08:14:59 +11:00
exception_helper.c	target/openrisc: Keep SR_CY and SR_OV in a separate variables	2017-02-14 08:14:59 +11:00
exception.c
exception.h
fpu_helper.c
gdbstub.c	target/openrisc: Keep SR_F in a separate variable	2017-02-14 08:14:59 +11:00
helper.h	target/openrisc: Set flags on helpers	2017-02-14 08:14:59 +11:00
interrupt_helper.c	target/openrisc: Keep SR_F in a separate variable	2017-02-14 08:14:59 +11:00
interrupt.c	target/openrisc: Keep SR_F in a separate variable	2017-02-14 08:14:59 +11:00
machine.c	target/openrisc: Keep SR_F in a separate variable	2017-02-14 08:14:59 +11:00
Makefile.objs	target/openrisc: Streamline arithmetic and OVE	2017-02-14 08:14:59 +11:00
mmu_helper.c
mmu.c	target/openrisc: Implement lwa, swa	2017-02-14 08:14:59 +11:00
sys_helper.c	target/openrisc: Keep SR_F in a separate variable	2017-02-14 08:14:59 +11:00
translate.c	target/openrisc: Enable trap, csync, msync, psync for user mode	2017-02-14 08:15:00 +11:00