3295186083
ICCICR/GICC_CTLR is banked in GICv1 implementations with Security Extensions or in GICv2 in independent from Security Extensions. This makes it possible to enable forwarding of interrupts from the CPU interfaces to the connected processors for Group0 and Group1. We also allow to set additional bits like AckCtl and FIQEn by changing the type from bool to uint32. Since the field does not only store the enable bit anymore and since we are touching the vmstate, we use the opportunity to rename the field to cpu_ctlr. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-9-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-9-git-send-email-greg.bellows@linaro.org [PMM: rewrote to store state in a single uint32_t rather than keeping the NS and S banked variants separate; this considerably simplifies the get/set functions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
190 lines
6.2 KiB
C
190 lines
6.2 KiB
C
/*
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* ARM GIC support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "gic_internal.h"
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static void gic_pre_save(void *opaque)
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{
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GICState *s = (GICState *)opaque;
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ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
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if (c->pre_save) {
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c->pre_save(s);
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}
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}
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static int gic_post_load(void *opaque, int version_id)
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{
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GICState *s = (GICState *)opaque;
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ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
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if (c->post_load) {
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c->post_load(s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_gic_irq_state = {
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.name = "arm_gic_irq_state",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(enabled, gic_irq_state),
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VMSTATE_UINT8(pending, gic_irq_state),
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VMSTATE_UINT8(active, gic_irq_state),
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VMSTATE_UINT8(level, gic_irq_state),
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VMSTATE_BOOL(model, gic_irq_state),
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VMSTATE_BOOL(edge_trigger, gic_irq_state),
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VMSTATE_UINT8(group, gic_irq_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_gic = {
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.name = "arm_gic",
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.version_id = 10,
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.minimum_version_id = 10,
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.pre_save = gic_pre_save,
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.post_load = gic_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ctlr, GICState),
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VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
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VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
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vmstate_gic_irq_state, gic_irq_state),
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VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
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VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
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VMSTATE_UINT16_2DARRAY(last_active, GICState, GIC_MAXIRQ, GIC_NCPU),
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VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
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VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
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VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU),
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VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
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VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
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VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static void arm_gic_common_realize(DeviceState *dev, Error **errp)
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{
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GICState *s = ARM_GIC_COMMON(dev);
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int num_irq = s->num_irq;
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if (s->num_cpu > GIC_NCPU) {
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error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
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s->num_cpu, GIC_NCPU);
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return;
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}
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s->num_irq += GIC_BASE_IRQ;
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if (s->num_irq > GIC_MAXIRQ) {
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error_setg(errp,
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"requested %u interrupt lines exceeds GIC maximum %d",
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num_irq, GIC_MAXIRQ);
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return;
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}
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/* ITLinesNumber is represented as (N / 32) - 1 (see
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* gic_dist_readb) so this is an implementation imposed
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* restriction, not an architectural one:
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*/
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if (s->num_irq < 32 || (s->num_irq % 32)) {
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error_setg(errp,
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"%d interrupt lines unsupported: not divisible by 32",
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num_irq);
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return;
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}
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if (s->security_extn &&
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(s->revision == REV_11MPCORE || s->revision == REV_NVIC)) {
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error_setg(errp, "this GIC revision does not implement "
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"the security extensions");
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return;
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}
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}
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static void arm_gic_common_reset(DeviceState *dev)
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{
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GICState *s = ARM_GIC_COMMON(dev);
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int i;
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memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < s->num_cpu; i++) {
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if (s->revision == REV_11MPCORE) {
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s->priority_mask[i] = 0xf0;
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} else {
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s->priority_mask[i] = 0;
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}
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s->current_pending[i] = 1023;
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s->running_irq[i] = 1023;
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s->running_priority[i] = 0x100;
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s->cpu_ctlr[i] = 0;
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}
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for (i = 0; i < GIC_NR_SGIS; i++) {
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GIC_SET_ENABLED(i, ALL_CPU_MASK);
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GIC_SET_EDGE_TRIGGER(i);
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}
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if (s->num_cpu == 1) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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for (i = 0; i < GIC_MAXIRQ; i++) {
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s->irq_target[i] = 1;
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}
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}
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s->ctlr = 0;
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}
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static Property arm_gic_common_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
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/* Revision can be 1 or 2 for GIC architecture specification
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* versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
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* (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
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*/
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DEFINE_PROP_UINT32("revision", GICState, revision, 1),
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/* True if the GIC should implement the security extensions */
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DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void arm_gic_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = arm_gic_common_reset;
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dc->realize = arm_gic_common_realize;
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dc->props = arm_gic_common_properties;
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dc->vmsd = &vmstate_gic;
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}
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static const TypeInfo arm_gic_common_type = {
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.name = TYPE_ARM_GIC_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GICState),
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.class_size = sizeof(ARMGICCommonClass),
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.class_init = arm_gic_common_class_init,
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.abstract = true,
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};
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static void register_types(void)
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{
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type_register_static(&arm_gic_common_type);
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}
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type_init(register_types)
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