467 lines
12 KiB
C
467 lines
12 KiB
C
/*
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* QEMU 8259 interrupt controller emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/intc/i8259.h"
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#include "hw/irq.h"
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#include "hw/isa/isa.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "hw/isa/i8259_internal.h"
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#include "trace.h"
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#include "qom/object.h"
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/* debug PIC */
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//#define DEBUG_PIC
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//#define DEBUG_IRQ_LATENCY
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#define TYPE_I8259 "isa-i8259"
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typedef struct PICClass PICClass;
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DECLARE_CLASS_CHECKERS(PICClass, PIC,
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TYPE_I8259)
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/**
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* PICClass:
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* @parent_realize: The parent's realizefn.
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*/
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struct PICClass {
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PICCommonClass parent_class;
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DeviceRealize parent_realize;
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};
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#ifdef DEBUG_IRQ_LATENCY
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static int64_t irq_time[16];
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#endif
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DeviceState *isa_pic;
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static PICCommonState *slave_pic;
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/* return the highest priority found in mask (highest = smallest
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number). Return 8 if no irq */
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static int get_priority(PICCommonState *s, int mask)
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{
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int priority;
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if (mask == 0) {
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return 8;
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}
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priority = 0;
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while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) {
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priority++;
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}
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return priority;
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}
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/* return the pic wanted interrupt. return -1 if none */
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static int pic_get_irq(PICCommonState *s)
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{
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int mask, cur_priority, priority;
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mask = s->irr & ~s->imr;
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priority = get_priority(s, mask);
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if (priority == 8) {
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return -1;
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}
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/* compute current priority. If special fully nested mode on the
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master, the IRQ coming from the slave is not taken into account
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for the priority computation. */
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mask = s->isr;
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if (s->special_mask) {
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mask &= ~s->imr;
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}
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if (s->special_fully_nested_mode && s->master) {
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mask &= ~(1 << 2);
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}
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cur_priority = get_priority(s, mask);
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if (priority < cur_priority) {
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/* higher priority found: an irq should be generated */
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return (priority + s->priority_add) & 7;
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} else {
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return -1;
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}
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}
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/* Update INT output. Must be called every time the output may have changed. */
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static void pic_update_irq(PICCommonState *s)
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{
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int irq;
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irq = pic_get_irq(s);
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if (irq >= 0) {
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trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add);
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qemu_irq_raise(s->int_out[0]);
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} else {
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qemu_irq_lower(s->int_out[0]);
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}
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}
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/* set irq level. If an edge is detected, then the IRR is set to 1 */
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static void pic_set_irq(void *opaque, int irq, int level)
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{
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PICCommonState *s = opaque;
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int mask = 1 << irq;
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int irq_index = s->master ? irq : irq + 8;
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trace_pic_set_irq(s->master, irq, level);
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pic_stat_update_irq(irq_index, level);
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#ifdef DEBUG_IRQ_LATENCY
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if (level) {
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irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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}
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#endif
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if (s->elcr & mask) {
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/* level triggered */
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if (level) {
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s->irr |= mask;
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s->last_irr |= mask;
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} else {
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s->irr &= ~mask;
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s->last_irr &= ~mask;
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}
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} else {
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/* edge triggered */
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if (level) {
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if ((s->last_irr & mask) == 0) {
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s->irr |= mask;
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}
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s->last_irr |= mask;
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} else {
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s->last_irr &= ~mask;
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}
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}
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pic_update_irq(s);
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}
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/* acknowledge interrupt 'irq' */
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static void pic_intack(PICCommonState *s, int irq)
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{
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if (s->auto_eoi) {
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if (s->rotate_on_auto_eoi) {
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s->priority_add = (irq + 1) & 7;
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}
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} else {
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s->isr |= (1 << irq);
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}
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/* We don't clear a level sensitive interrupt here */
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if (!(s->elcr & (1 << irq))) {
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s->irr &= ~(1 << irq);
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}
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pic_update_irq(s);
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}
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int pic_read_irq(DeviceState *d)
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{
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PICCommonState *s = PIC_COMMON(d);
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int irq, intno;
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irq = pic_get_irq(s);
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if (irq >= 0) {
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int irq2;
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if (irq == 2) {
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irq2 = pic_get_irq(slave_pic);
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if (irq2 >= 0) {
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pic_intack(slave_pic, irq2);
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} else {
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/* spurious IRQ on slave controller */
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irq2 = 7;
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}
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intno = slave_pic->irq_base + irq2;
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pic_intack(s, irq);
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irq = irq2 + 8;
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} else {
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intno = s->irq_base + irq;
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pic_intack(s, irq);
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}
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} else {
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/* spurious IRQ on host controller */
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irq = 7;
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intno = s->irq_base + irq;
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}
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#ifdef DEBUG_IRQ_LATENCY
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printf("IRQ%d latency=%0.3fus\n",
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irq,
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(double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
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irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND);
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#endif
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trace_pic_interrupt(irq, intno);
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return intno;
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}
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static void pic_init_reset(PICCommonState *s)
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{
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pic_reset_common(s);
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pic_update_irq(s);
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}
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static void pic_reset(DeviceState *dev)
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{
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PICCommonState *s = PIC_COMMON(dev);
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s->elcr = 0;
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pic_init_reset(s);
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}
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static void pic_ioport_write(void *opaque, hwaddr addr64,
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uint64_t val64, unsigned size)
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{
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PICCommonState *s = opaque;
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uint32_t addr = addr64;
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uint32_t val = val64;
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int priority, cmd, irq;
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trace_pic_ioport_write(s->master, addr, val);
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if (addr == 0) {
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if (val & 0x10) {
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pic_init_reset(s);
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s->init_state = 1;
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s->init4 = val & 1;
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s->single_mode = val & 2;
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if (val & 0x08) {
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qemu_log_mask(LOG_UNIMP,
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"i8259: level sensitive irq not supported\n");
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}
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} else if (val & 0x08) {
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if (val & 0x04) {
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s->poll = 1;
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}
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if (val & 0x02) {
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s->read_reg_select = val & 1;
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}
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if (val & 0x40) {
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s->special_mask = (val >> 5) & 1;
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}
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} else {
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cmd = val >> 5;
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switch (cmd) {
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case 0:
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case 4:
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s->rotate_on_auto_eoi = cmd >> 2;
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break;
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case 1: /* end of interrupt */
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case 5:
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priority = get_priority(s, s->isr);
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if (priority != 8) {
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irq = (priority + s->priority_add) & 7;
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s->isr &= ~(1 << irq);
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if (cmd == 5) {
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s->priority_add = (irq + 1) & 7;
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}
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pic_update_irq(s);
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}
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break;
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case 3:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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pic_update_irq(s);
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break;
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case 6:
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s->priority_add = (val + 1) & 7;
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pic_update_irq(s);
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break;
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case 7:
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irq = val & 7;
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s->isr &= ~(1 << irq);
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s->priority_add = (irq + 1) & 7;
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pic_update_irq(s);
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break;
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default:
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/* no operation */
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break;
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}
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}
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} else {
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switch (s->init_state) {
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case 0:
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/* normal mode */
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s->imr = val;
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pic_update_irq(s);
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break;
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case 1:
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s->irq_base = val & 0xf8;
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s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
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break;
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case 2:
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if (s->init4) {
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s->init_state = 3;
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} else {
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s->init_state = 0;
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}
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break;
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case 3:
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s->special_fully_nested_mode = (val >> 4) & 1;
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s->auto_eoi = (val >> 1) & 1;
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s->init_state = 0;
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break;
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}
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}
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}
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static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PICCommonState *s = opaque;
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int ret;
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if (s->poll) {
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ret = pic_get_irq(s);
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if (ret >= 0) {
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pic_intack(s, ret);
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ret |= 0x80;
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} else {
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ret = 0;
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}
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s->poll = 0;
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} else {
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if (addr == 0) {
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if (s->read_reg_select) {
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ret = s->isr;
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} else {
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ret = s->irr;
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}
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} else {
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ret = s->imr;
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}
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}
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trace_pic_ioport_read(s->master, addr, ret);
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return ret;
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}
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int pic_get_output(DeviceState *d)
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{
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PICCommonState *s = PIC_COMMON(d);
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return (pic_get_irq(s) >= 0);
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}
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static void elcr_ioport_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PICCommonState *s = opaque;
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s->elcr = val & s->elcr_mask;
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}
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static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PICCommonState *s = opaque;
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return s->elcr;
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}
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static const MemoryRegionOps pic_base_ioport_ops = {
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.read = pic_ioport_read,
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.write = pic_ioport_write,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static const MemoryRegionOps pic_elcr_ioport_ops = {
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.read = elcr_ioport_read,
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.write = elcr_ioport_write,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static void pic_realize(DeviceState *dev, Error **errp)
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{
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PICCommonState *s = PIC_COMMON(dev);
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PICClass *pc = PIC_GET_CLASS(dev);
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memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s,
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"pic", 2);
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memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s,
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"elcr", 1);
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qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out));
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qdev_init_gpio_in(dev, pic_set_irq, 8);
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pc->parent_realize(dev, errp);
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}
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qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
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{
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qemu_irq *irq_set;
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DeviceState *dev;
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ISADevice *isadev;
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int i;
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irq_set = g_new0(qemu_irq, ISA_NUM_IRQS);
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isadev = i8259_init_chip(TYPE_I8259, bus, true);
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dev = DEVICE(isadev);
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qdev_connect_gpio_out(dev, 0, parent_irq);
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for (i = 0 ; i < 8; i++) {
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irq_set[i] = qdev_get_gpio_in(dev, i);
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}
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isa_pic = dev;
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isadev = i8259_init_chip(TYPE_I8259, bus, false);
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dev = DEVICE(isadev);
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qdev_connect_gpio_out(dev, 0, irq_set[2]);
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for (i = 0 ; i < 8; i++) {
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irq_set[i + 8] = qdev_get_gpio_in(dev, i);
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}
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slave_pic = PIC_COMMON(dev);
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return irq_set;
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}
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static void i8259_class_init(ObjectClass *klass, void *data)
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{
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PICClass *k = PIC_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_parent_realize(dc, pic_realize, &k->parent_realize);
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dc->reset = pic_reset;
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}
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static const TypeInfo i8259_info = {
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.name = TYPE_I8259,
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.instance_size = sizeof(PICCommonState),
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.parent = TYPE_PIC_COMMON,
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.class_init = i8259_class_init,
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.class_size = sizeof(PICClass),
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};
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static void pic_register_types(void)
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{
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type_register_static(&i8259_info);
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}
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type_init(pic_register_types)
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