6e42be7cd1
A transition from CPUFooState to FooCPU can be considered safe,
just like FooCPU::env access in the opposite direction.
The only benefit of the FOO_CPU() casts would be protection against
bogus CPUFooState pointers, but then surrounding code would likely
break, too.
This should slightly improve interrupt etc. performance when going from
CPUFooState to FooCPU.
For any additional CPU() casts see 3556c233d9
(qom: allow turning cast debugging off).
Reported-by: Anthony Liguori <aliguori@us.ibm.com>
Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
151 lines
4.4 KiB
C
151 lines
4.4 KiB
C
/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_ARM_CPU_QOM_H
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#define QEMU_ARM_CPU_QOM_H
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#include "qom/cpu.h"
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#define TYPE_ARM_CPU "arm-cpu"
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#define ARM_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
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#define ARM_CPU(obj) \
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OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
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#define ARM_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
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/**
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* ARMCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* An ARM CPU model.
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*/
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typedef struct ARMCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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} ARMCPUClass;
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/**
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* ARMCPU:
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* @env: #CPUARMState
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*
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* An ARM CPU core.
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*/
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typedef struct ARMCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUARMState env;
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/* Coprocessor information */
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GHashTable *cp_regs;
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/* For marshalling (mostly coprocessor) register state between the
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* kernel and QEMU (for KVM) and between two QEMUs (for migration),
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* we use these arrays.
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*/
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/* List of register indexes managed via these arrays; (full KVM style
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* 64 bit indexes, not CPRegInfo 32 bit indexes)
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*/
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uint64_t *cpreg_indexes;
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/* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
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uint64_t *cpreg_values;
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/* When using KVM, keeps a copy of the initial state of the VCPU,
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* so that on reset we can feed the reset values back into the kernel.
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*/
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uint64_t *cpreg_reset_values;
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/* Length of the indexes, values, reset_values arrays */
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int32_t cpreg_array_len;
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/* These are used only for migration: incoming data arrives in
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* these fields and is sanity checked in post_load before copying
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* to the working data structures above.
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*/
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uint64_t *cpreg_vmstate_indexes;
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uint64_t *cpreg_vmstate_values;
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int32_t cpreg_vmstate_array_len;
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/* The instance init functions for implementation-specific subclasses
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* set these fields to specify the implementation-dependent values of
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* various constant registers and reset values of non-constant
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* registers.
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* Some of these might become QOM properties eventually.
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* Field names match the official register names as defined in the
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* ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
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* is used for reset values of non-constant registers; no reset_
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* prefix means a constant register.
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*/
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uint32_t midr;
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uint32_t reset_fpsid;
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uint32_t mvfr0;
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uint32_t mvfr1;
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uint32_t ctr;
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uint32_t reset_sctlr;
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uint32_t id_pfr0;
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uint32_t id_pfr1;
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uint32_t id_dfr0;
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uint32_t id_afr0;
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uint32_t id_mmfr0;
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uint32_t id_mmfr1;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_isar0;
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uint32_t id_isar1;
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uint32_t id_isar2;
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uint32_t id_isar3;
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uint32_t id_isar4;
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uint32_t id_isar5;
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uint32_t clidr;
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/* The elements of this array are the CCSIDR values for each cache,
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* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
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*/
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uint32_t ccsidr[16];
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uint32_t reset_cbar;
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uint32_t reset_auxcr;
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} ARMCPU;
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static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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{
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return container_of(env, ARMCPU, env);
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}
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#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
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#define ENV_OFFSET offsetof(ARMCPU, env)
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_arm_cpu;
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#endif
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void register_cp_regs_for_features(ARMCPU *cpu);
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void init_cpreg_list(ARMCPU *cpu);
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void arm_cpu_do_interrupt(CPUState *cpu);
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void arm_v7m_cpu_do_interrupt(CPUState *cpu);
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void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags);
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#endif
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