c2ecb424fb
GBPA register can be used to globally abort all transactions. It is described in the SMMU manual in "6.3.14 SMMU_GBPA". ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to be zero(Do not abort incoming transactions). Other fields have default values of Use Incoming. If UPDATE is not set, the write is ignored. This is the only permitted behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) As this patch adds a new state to the SMMU (GBPA), it is added in a new subsection for forward migration compatibility. GBPA is only migrated if its value is different from the reset value. It does this to be backward migration compatible if SW didn't write the register. Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230214094009.2445653-1-smostafa@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
87 lines
2.0 KiB
C
87 lines
2.0 KiB
C
/*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_SMMUV3_H
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#define HW_ARM_SMMUV3_H
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#include "hw/arm/smmu-common.h"
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#include "qom/object.h"
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#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
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typedef struct SMMUQueue {
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uint64_t base; /* base register */
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uint32_t prod;
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uint32_t cons;
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uint8_t entry_size;
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uint8_t log2size;
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} SMMUQueue;
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struct SMMUv3State {
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SMMUState smmu_state;
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uint32_t features;
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uint8_t sid_size;
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uint8_t sid_split;
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uint32_t idr[6];
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uint32_t iidr;
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uint32_t aidr;
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uint32_t cr[3];
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uint32_t cr0ack;
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uint32_t statusr;
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uint32_t gbpa;
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uint32_t irq_ctrl;
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uint32_t gerror;
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uint32_t gerrorn;
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uint64_t gerror_irq_cfg0;
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uint32_t gerror_irq_cfg1;
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uint32_t gerror_irq_cfg2;
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uint64_t strtab_base;
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uint32_t strtab_base_cfg;
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uint64_t eventq_irq_cfg0;
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uint32_t eventq_irq_cfg1;
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uint32_t eventq_irq_cfg2;
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SMMUQueue eventq, cmdq;
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qemu_irq irq[4];
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QemuMutex mutex;
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};
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typedef enum {
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SMMU_IRQ_EVTQ,
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SMMU_IRQ_PRIQ,
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SMMU_IRQ_CMD_SYNC,
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SMMU_IRQ_GERROR,
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} SMMUIrq;
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struct SMMUv3Class {
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/*< private >*/
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SMMUBaseClass smmu_base_class;
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/*< public >*/
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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#define TYPE_ARM_SMMUV3 "arm-smmuv3"
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OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
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#endif
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