050c2ea07b
The Arm Cortex-M System Design Kit includes a simple watchdog module based on a 32-bit down-counter. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
327 lines
9.3 KiB
C
327 lines
9.3 KiB
C
/*
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* ARM CMSDK APB watchdog emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "APB watchdog" which is part of the Cortex-M
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* System Design Kit (CMSDK) and documented in the Cortex-M System
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* Design Kit Technical Reference Manual (ARM DDI0479C):
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* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "qemu/main-loop.h"
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#include "sysemu/watchdog.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/watchdog/cmsdk-apb-watchdog.h"
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REG32(WDOGLOAD, 0x0)
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REG32(WDOGVALUE, 0x4)
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REG32(WDOGCONTROL, 0x8)
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FIELD(WDOGCONTROL, INTEN, 0, 1)
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FIELD(WDOGCONTROL, RESEN, 1, 1)
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#define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \
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R_WDOGCONTROL_RESEN_MASK)
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REG32(WDOGINTCLR, 0xc)
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REG32(WDOGRIS, 0x10)
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FIELD(WDOGRIS, INT, 0, 1)
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REG32(WDOGMIS, 0x14)
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REG32(WDOGLOCK, 0xc00)
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#define WDOG_UNLOCK_VALUE 0x1ACCE551
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REG32(WDOGITCR, 0xf00)
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FIELD(WDOGITCR, ENABLE, 0, 1)
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#define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK
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REG32(WDOGITOP, 0xf04)
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FIELD(WDOGITOP, WDOGRES, 0, 1)
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FIELD(WDOGITOP, WDOGINT, 1, 1)
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#define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \
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R_WDOGITOP_WDOGINT_MASK)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* PID/CID values */
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static const int watchdog_id[] = {
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0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
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0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
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0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
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};
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static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)
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{
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/* Return masked interrupt status */
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return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK);
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}
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static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s)
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{
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/* Return masked reset status */
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return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK);
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}
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static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)
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{
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bool wdogint;
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bool wdogres;
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if (s->itcr) {
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wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;
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wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;
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} else {
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wdogint = cmsdk_apb_watchdog_intstatus(s);
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wdogres = cmsdk_apb_watchdog_resetstatus(s);
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}
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qemu_set_irq(s->wdogint, wdogint);
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if (wdogres) {
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watchdog_perform_action();
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}
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}
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static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
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uint64_t r;
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switch (offset) {
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case A_WDOGLOAD:
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r = ptimer_get_limit(s->timer);
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break;
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case A_WDOGVALUE:
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r = ptimer_get_count(s->timer);
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break;
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case A_WDOGCONTROL:
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r = s->control;
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break;
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case A_WDOGRIS:
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r = s->intstatus;
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break;
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case A_WDOGMIS:
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r = cmsdk_apb_watchdog_intstatus(s);
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break;
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case A_WDOGLOCK:
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r = s->lock;
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break;
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case A_WDOGITCR:
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r = s->itcr;
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break;
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case A_PID4 ... A_CID3:
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r = watchdog_id[(offset - A_PID4) / 4];
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break;
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case A_WDOGINTCLR:
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case A_WDOGITOP:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB watchdog read: read of WO offset %x\n",
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(int)offset);
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r = 0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB watchdog read: bad offset %x\n", (int)offset);
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r = 0;
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break;
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}
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trace_cmsdk_apb_watchdog_read(offset, r, size);
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return r;
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}
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static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
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trace_cmsdk_apb_watchdog_write(offset, value, size);
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if (s->lock && offset != A_WDOGLOCK) {
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/* Write access is disabled via WDOGLOCK */
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB watchdog write: write to locked watchdog\n");
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return;
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}
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switch (offset) {
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case A_WDOGLOAD:
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/*
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* Reset the load value and the current count, and make sure
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* we're counting.
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*/
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ptimer_set_limit(s->timer, value, 1);
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ptimer_run(s->timer, 0);
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break;
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case A_WDOGCONTROL:
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s->control = value & R_WDOGCONTROL_VALID_MASK;
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cmsdk_apb_watchdog_update(s);
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break;
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case A_WDOGINTCLR:
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s->intstatus = 0;
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ptimer_set_count(s->timer, ptimer_get_limit(s->timer));
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cmsdk_apb_watchdog_update(s);
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break;
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case A_WDOGLOCK:
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s->lock = (value != WDOG_UNLOCK_VALUE);
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break;
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case A_WDOGITCR:
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s->itcr = value & R_WDOGITCR_VALID_MASK;
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cmsdk_apb_watchdog_update(s);
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break;
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case A_WDOGITOP:
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s->itop = value & R_WDOGITOP_VALID_MASK;
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cmsdk_apb_watchdog_update(s);
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break;
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case A_WDOGVALUE:
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case A_WDOGRIS:
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case A_WDOGMIS:
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case A_PID4 ... A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB watchdog write: write to RO offset 0x%x\n",
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(int)offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"CMSDK APB watchdog write: bad offset 0x%x\n",
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(int)offset);
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break;
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}
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}
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static const MemoryRegionOps cmsdk_apb_watchdog_ops = {
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.read = cmsdk_apb_watchdog_read,
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.write = cmsdk_apb_watchdog_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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/* byte/halfword accesses are just zero-padded on reads and writes */
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static void cmsdk_apb_watchdog_tick(void *opaque)
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{
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CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
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if (!s->intstatus) {
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/* Count expired for the first time: raise interrupt */
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s->intstatus = R_WDOGRIS_INT_MASK;
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} else {
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/* Count expired for the second time: raise reset and stop clock */
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s->resetstatus = 1;
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ptimer_stop(s->timer);
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}
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cmsdk_apb_watchdog_update(s);
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}
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static void cmsdk_apb_watchdog_reset(DeviceState *dev)
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{
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CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
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trace_cmsdk_apb_watchdog_reset();
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s->control = 0;
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s->intstatus = 0;
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s->lock = 0;
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s->itcr = 0;
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s->itop = 0;
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s->resetstatus = 0;
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/* Set the limit and the count */
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ptimer_set_limit(s->timer, 0xffffffff, 1);
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ptimer_run(s->timer, 0);
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}
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static void cmsdk_apb_watchdog_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
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memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops,
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s, "cmsdk-apb-watchdog", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->wdogint);
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}
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static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
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{
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CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
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QEMUBH *bh;
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if (s->wdogclk_frq == 0) {
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error_setg(errp,
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"CMSDK APB watchdog: wdogclk-frq property must be set");
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return;
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}
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bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s);
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s->timer = ptimer_init(bh,
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PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
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PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
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PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
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PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
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ptimer_set_freq(s->timer, s->wdogclk_frq);
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}
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static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
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.name = "cmsdk-apb-watchdog",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
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VMSTATE_UINT32(control, CMSDKAPBWatchdog),
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VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
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VMSTATE_UINT32(lock, CMSDKAPBWatchdog),
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VMSTATE_UINT32(itcr, CMSDKAPBWatchdog),
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VMSTATE_UINT32(itop, CMSDKAPBWatchdog),
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VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property cmsdk_apb_watchdog_properties[] = {
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DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = cmsdk_apb_watchdog_realize;
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dc->vmsd = &cmsdk_apb_watchdog_vmstate;
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dc->reset = cmsdk_apb_watchdog_reset;
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dc->props = cmsdk_apb_watchdog_properties;
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}
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static const TypeInfo cmsdk_apb_watchdog_info = {
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.name = TYPE_CMSDK_APB_WATCHDOG,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(CMSDKAPBWatchdog),
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.instance_init = cmsdk_apb_watchdog_init,
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.class_init = cmsdk_apb_watchdog_class_init,
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};
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static void cmsdk_apb_watchdog_register_types(void)
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{
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type_register_static(&cmsdk_apb_watchdog_info);
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}
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type_init(cmsdk_apb_watchdog_register_types);
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