333b9c8a68
The AST2500 SoC family changes the runtime behaviour of the hardware strapping register (SCU70) to write-1-set/write-1-clear, with write-1-clear implemented on the "read-only" SoC revision register (SCU7C). For the the AST2400, the hardware strapping is runtime-configured with read-modify-write semantics. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20180709143524.17480-1-andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
301 lines
12 KiB
C
301 lines
12 KiB
C
/*
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* ASPEED System Control Unit
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_SCU_H
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#define ASPEED_SCU_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_SCU "aspeed.scu"
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#define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU)
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#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
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typedef struct AspeedSCUState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t regs[ASPEED_SCU_NR_REGS];
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uint32_t silicon_rev;
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uint32_t hw_strap1;
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uint32_t hw_strap2;
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uint32_t hw_prot_key;
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uint32_t clkin;
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uint32_t hpll;
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uint32_t apb_freq;
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} AspeedSCUState;
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#define AST2400_A0_SILICON_REV 0x02000303U
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#define AST2400_A1_SILICON_REV 0x02010303U
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#define AST2500_A0_SILICON_REV 0x04000303U
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#define AST2500_A1_SILICON_REV 0x04010303U
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#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
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extern bool is_supported_silicon_rev(uint32_t silicon_rev);
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#define ASPEED_SCU_PROT_KEY 0x1688A8A8
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/*
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* Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
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* were added.
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*
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* Original header file :
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* arch/arm/mach-aspeed/include/mach/regs-scu.h
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*
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* Copyright (C) 2012-2020 ASPEED Technology Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* History :
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* 1. 2012/12/29 Ryan Chen Create
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*/
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/* SCU08 Clock Selection Register
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*
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* 31 Enable Video Engine clock dynamic slow down
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* 30:28 Video Engine clock slow down setting
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* 27 2D Engine GCLK clock source selection
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* 26 2D Engine GCLK clock throttling enable
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* 25:23 APB PCLK divider selection
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* 22:20 LPC Host LHCLK divider selection
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* 19 LPC Host LHCLK clock generation/output enable control
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* 18:16 MAC AHB bus clock divider selection
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* 15 SD/SDIO clock running enable
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* 14:12 SD/SDIO divider selection
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* 11 Reserved
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* 10:8 Video port output clock delay control bit
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* 7 ARM CPU/AHB clock slow down enable
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* 6:4 ARM CPU/AHB clock slow down setting
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* 3:2 ECLK clock source selection
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* 1 CPU/AHB clock slow down idle timer
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* 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
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*/
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#define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
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/* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
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*
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* 18 H-PLL parameter selection
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* 0: Select H-PLL by strapping resistors
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* 1: Select H-PLL by the programmed registers (SCU24[17:0])
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* 17 Enable H-PLL bypass mode
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* 16 Turn off H-PLL
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* 10:5 H-PLL Numerator
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* 4 H-PLL Output Divider
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* 3:0 H-PLL Denumerator
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*
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* (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
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*/
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#define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18)
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#define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
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#define SCU_AST2400_H_PLL_OFF (0x1 << 16)
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/* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
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*
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* 21 Enable H-PLL reset
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* 20 Enable H-PLL bypass mode
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* 19 Turn off H-PLL
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* 18:13 H-PLL Post Divider
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* 12:5 H-PLL Numerator (M)
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* 4:0 H-PLL Denumerator (N)
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*
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* (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
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*
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* The default frequency is 792Mhz when CLKIN = 24MHz
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*/
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#define SCU_H_PLL_BYPASS_EN (0x1 << 20)
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#define SCU_H_PLL_OFF (0x1 << 19)
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/* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)
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*
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* 31:29 Software defined strapping registers
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* 28:27 DRAM size setting (for VGA driver use)
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* 26:24 DRAM configuration setting
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* 23 Enable 25 MHz reference clock input
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* 22 Enable GPIOE pass-through mode
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* 21 Enable GPIOD pass-through mode
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* 20 Disable LPC to decode SuperIO 0x2E/0x4E address
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* 19 Disable ACPI function
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* 23,18 Clock source selection
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* 17 Enable BMC 2nd boot watchdog timer
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* 16 SuperIO configuration address selection
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* 15 VGA Class Code selection
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* 14 Enable LPC dedicated reset pin function
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* 13:12 SPI mode selection
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* 11:10 CPU/AHB clock frequency ratio selection
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* 9:8 H-PLL default clock frequency selection
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* 7 Define MAC#2 interface
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* 6 Define MAC#1 interface
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* 5 Enable VGA BIOS ROM
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* 4 Boot flash memory extended option
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* 3:2 VGA memory size selection
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* 1:0 BMC CPU boot code selection
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*/
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#define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29)
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#define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29)
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#define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27)
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#define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
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#define DRAM_SIZE_64MB 0
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#define DRAM_SIZE_128MB 1
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#define DRAM_SIZE_256MB 2
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#define DRAM_SIZE_512MB 3
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#define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24)
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#define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24)
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#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
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#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
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#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
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#define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19)
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/* bit 23, 18 [1,0] */
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#define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \
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| (((x) & 0x1) << 18))
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#define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
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| (((x) >> 18) & 0x1))
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#define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
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#define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
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#define AST2400_CLK_24M_IN 0
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#define AST2400_CLK_48M_IN 1
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#define AST2400_CLK_25M_IN_24M_USB_CKI 2
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#define AST2400_CLK_25M_IN_48M_USB_CKI 3
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#define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18)
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#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
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#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
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#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
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#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14)
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#define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12)
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#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12)
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#define SCU_HW_STRAP_SPI_DIS 0
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#define SCU_HW_STRAP_SPI_MASTER 1
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#define SCU_HW_STRAP_SPI_M_S_EN 2
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#define SCU_HW_STRAP_SPI_PASS_THROUGH 3
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#define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10)
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#define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3)
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#define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10)
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#define AST2400_CPU_AHB_RATIO_1_1 0
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#define AST2400_CPU_AHB_RATIO_2_1 1
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#define AST2400_CPU_AHB_RATIO_4_1 2
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#define AST2400_CPU_AHB_RATIO_3_1 3
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#define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3)
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#define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8)
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#define AST2400_CPU_384MHZ 0
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#define AST2400_CPU_360MHZ 1
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#define AST2400_CPU_336MHZ 2
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#define AST2400_CPU_408MHZ 3
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#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7)
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#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6)
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#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5)
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#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4)
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#define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3)
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#define SCU_HW_STRAP_VGA_MASK (0x3 << 2)
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#define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2)
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#define VGA_8M_DRAM 0
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#define VGA_16M_DRAM 1
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#define VGA_32M_DRAM 2
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#define VGA_64M_DRAM 3
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#define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x)
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#define AST2400_NOR_BOOT 0
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#define AST2400_NAND_BOOT 1
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#define AST2400_SPI_BOOT 2
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#define AST2400_DIS_BOOT 3
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/*
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* SCU70 Hardware strapping register definition (for Aspeed AST2500
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* SoC and higher)
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*
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* 31 Enable SPI Flash Strap Auto Fetch Mode
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* 30 Enable GPIO Strap Mode
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* 29 Select UART Debug Port
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* 28 Reserved (1)
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* 27 Enable fast reset mode for ARM ICE debugger
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* 26 Enable eSPI flash mode
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* 25 Enable eSPI mode
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* 24 Select DDR4 SDRAM
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* 23 Select 25 MHz reference clock input mode
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* 22 Enable GPIOE pass-through mode
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* 21 Enable GPIOD pass-through mode
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* 20 Disable LPC to decode SuperIO 0x2E/0x4E address
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* 19 Enable ACPI function
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* 18 Select USBCKI input frequency
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* 17 Enable BMC 2nd boot watchdog timer
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* 16 SuperIO configuration address selection
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* 15 VGA Class Code selection
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* 14 Select dedicated LPC reset input
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* 13:12 SPI mode selection
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* 11:9 AXI/AHB clock frequency ratio selection
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* 8 Reserved (0)
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* 7 Define MAC#2 interface
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* 6 Define MAC#1 interface
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* 5 Enable dedicated VGA BIOS ROM
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* 4 Reserved (0)
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* 3:2 VGA memory size selection
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* 1 Reserved (1)
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* 0 Disable CPU boot
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*/
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#define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31)
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#define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30)
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#define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29)
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#define UART_DEBUG_UART1 0
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#define UART_DEBUG_UART5 1
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#define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28)
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#define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27)
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#define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)
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#define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25)
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#define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24)
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#define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19)
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#define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18)
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#define USBCKI_FREQ_24MHZ 0
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#define USBCKI_FREQ_28MHZ 1
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#define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9)
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#define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7)
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#define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9)
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#define AXI_AHB_RATIO_UNDEFINED 0
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#define AXI_AHB_RATIO_2_1 1
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#define AXI_AHB_RATIO_3_1 2
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#define AXI_AHB_RATIO_4_1 3
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#define AXI_AHB_RATIO_5_1 4
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#define AXI_AHB_RATIO_6_1 5
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#define AXI_AHB_RATIO_7_1 6
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#define AXI_AHB_RATIO_8_1 7
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#define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1)
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#define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0)
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#define AST2500_HW_STRAP1_DEFAULTS ( \
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SCU_AST2500_HW_STRAP_RESERVED28 | \
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SCU_HW_STRAP_2ND_BOOT_WDT | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2500_HW_STRAP_RESERVED1)
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#endif /* ASPEED_SCU_H */
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