Michael Clark 244df42133

RISC-V: Replace __builtin_popcount with ctpop8 in PLIC ...

The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-03-19 05:14:38 -07:00

..

Kconfig

riscv/Kconfig: enable PCI_DEVICES

2019-03-11 16:33:49 +01:00

Makefile.objs

hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards

2019-02-05 16:50:20 +01:00

riscv_hart.c

riscv_hart: Fix crash when introspecting the device

2018-07-19 09:05:48 -07:00

riscv_htif.c

hw: Do not include "exec/address-spaces.h" if it is not necessary

2018-06-01 14:15:10 +02:00

sifive_clint.c

RISC-V: Fix CLINT timecmp low 32-bit writes

2018-12-20 12:08:43 -08:00

sifive_e.c

riscv: Ensure the kernel start address is correctly cast

2019-02-11 15:56:22 -08:00

sifive_plic.c

RISC-V: Replace __builtin_popcount with ctpop8 in PLIC

2019-03-19 05:14:38 -07:00

sifive_prci.c

SiFive RISC-V PRCI Block

2018-03-07 08:30:28 +13:00

sifive_test.c

SiFive RISC-V Test Finisher

2018-03-07 08:30:28 +13:00

sifive_u.c

riscv: Ensure the kernel start address is correctly cast

2019-02-11 15:56:22 -08:00

sifive_uart.c

sifive_uart: Implement interrupt pending register

2018-12-20 12:08:43 -08:00

spike.c

riscv: Ensure the kernel start address is correctly cast

2019-02-11 15:56:22 -08:00

virt.c

riscv: Ensure the kernel start address is correctly cast

2019-02-11 15:56:22 -08:00