2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
264 lines
7.1 KiB
C
264 lines
7.1 KiB
C
/*
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* ARMV7M System emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "sysbus.h"
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#include "arm-misc.h"
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#include "sysemu.h"
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#include "loader.h"
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#include "elf.h"
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/* Bitbanded IO. Each word corresponds to a single bit. */
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/* Get the byte address of the real memory for a bitband acess. */
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static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
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{
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uint32_t res;
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res = *(uint32_t *)opaque;
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res |= (addr & 0x1ffffff) >> 5;
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return res;
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}
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static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
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{
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uint8_t v;
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cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
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return (v & (1 << ((offset >> 2) & 7))) != 0;
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}
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static void bitband_writeb(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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uint32_t addr;
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uint8_t mask;
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uint8_t v;
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addr = bitband_addr(opaque, offset);
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mask = (1 << ((offset >> 2) & 7));
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cpu_physical_memory_read(addr, &v, 1);
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if (value & 1)
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v |= mask;
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else
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v &= ~mask;
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cpu_physical_memory_write(addr, &v, 1);
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}
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static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
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{
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uint32_t addr;
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uint16_t mask;
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uint16_t v;
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addr = bitband_addr(opaque, offset) & ~1;
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mask = (1 << ((offset >> 2) & 15));
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mask = tswap16(mask);
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cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
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return (v & mask) != 0;
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}
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static void bitband_writew(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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uint32_t addr;
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uint16_t mask;
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uint16_t v;
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addr = bitband_addr(opaque, offset) & ~1;
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mask = (1 << ((offset >> 2) & 15));
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mask = tswap16(mask);
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cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
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if (value & 1)
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v |= mask;
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else
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v &= ~mask;
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cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
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}
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static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
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{
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uint32_t addr;
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uint32_t mask;
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uint32_t v;
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addr = bitband_addr(opaque, offset) & ~3;
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mask = (1 << ((offset >> 2) & 31));
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mask = tswap32(mask);
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cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
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return (v & mask) != 0;
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}
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static void bitband_writel(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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uint32_t addr;
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uint32_t mask;
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uint32_t v;
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addr = bitband_addr(opaque, offset) & ~3;
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mask = (1 << ((offset >> 2) & 31));
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mask = tswap32(mask);
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cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
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if (value & 1)
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v |= mask;
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else
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v &= ~mask;
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cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
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}
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static CPUReadMemoryFunc * const bitband_readfn[] = {
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bitband_readb,
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bitband_readw,
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bitband_readl
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};
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static CPUWriteMemoryFunc * const bitband_writefn[] = {
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bitband_writeb,
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bitband_writew,
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bitband_writel
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};
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typedef struct {
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SysBusDevice busdev;
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uint32_t base;
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} BitBandState;
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static int bitband_init(SysBusDevice *dev)
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{
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BitBandState *s = FROM_SYSBUS(BitBandState, dev);
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int iomemtype;
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iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
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&s->base, DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, 0x02000000, iomemtype);
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return 0;
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}
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static void armv7m_bitband_init(void)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "ARM,bitband-memory");
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qdev_prop_set_uint32(dev, "base", 0x20000000);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x22000000);
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dev = qdev_create(NULL, "ARM,bitband-memory");
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qdev_prop_set_uint32(dev, "base", 0x40000000);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x42000000);
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}
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/* Board init. */
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static void armv7m_reset(void *opaque)
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{
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cpu_reset((CPUState *)opaque);
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}
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/* Init CPU and memory for a v7-M based board.
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flash_size and sram_size are in kb.
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Returns the NVIC array. */
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qemu_irq *armv7m_init(int flash_size, int sram_size,
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const char *kernel_filename, const char *cpu_model)
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{
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CPUState *env;
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DeviceState *nvic;
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/* FIXME: make this local state. */
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static qemu_irq pic[64];
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qemu_irq *cpu_pic;
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int image_size;
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uint64_t entry;
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uint64_t lowaddr;
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int i;
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int big_endian;
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flash_size *= 1024;
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sram_size *= 1024;
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if (!cpu_model)
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cpu_model = "cortex-m3";
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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#if 0
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/* > 32Mb SRAM gets complicated because it overlaps the bitband area.
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We don't have proper commandline options, so allocate half of memory
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as SRAM, up to a maximum of 32Mb, and the rest as code. */
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if (ram_size > (512 + 32) * 1024 * 1024)
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ram_size = (512 + 32) * 1024 * 1024;
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sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
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if (sram_size > 32 * 1024 * 1024)
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sram_size = 32 * 1024 * 1024;
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code_size = ram_size - sram_size;
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#endif
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/* Flash programming is done via the SCU, so pretend it is ROM. */
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cpu_register_physical_memory(0, flash_size,
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qemu_ram_alloc(NULL, "armv7m.flash",
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flash_size) | IO_MEM_ROM);
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cpu_register_physical_memory(0x20000000, sram_size,
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qemu_ram_alloc(NULL, "armv7m.sram",
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sram_size) | IO_MEM_RAM);
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armv7m_bitband_init();
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nvic = qdev_create(NULL, "armv7m_nvic");
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env->nvic = nvic;
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qdev_init_nofail(nvic);
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cpu_pic = arm_pic_init_cpu(env);
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sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
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for (i = 0; i < 64; i++) {
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pic[i] = qdev_get_gpio_in(nvic, i);
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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big_endian = 1;
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#else
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big_endian = 0;
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#endif
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image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
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NULL, big_endian, ELF_MACHINE, 1);
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if (image_size < 0) {
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image_size = load_image_targphys(kernel_filename, 0, flash_size);
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lowaddr = 0;
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}
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if (image_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* Hack to map an additional page of ram at the top of the address
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space. This stops qemu complaining about executing code outside RAM
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when returning from an exception. */
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cpu_register_physical_memory(0xfffff000, 0x1000,
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qemu_ram_alloc(NULL, "armv7m.hack",
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0x1000) | IO_MEM_RAM);
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qemu_register_reset(armv7m_reset, env);
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return pic;
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}
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static SysBusDeviceInfo bitband_info = {
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.init = bitband_init,
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.qdev.name = "ARM,bitband-memory",
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.qdev.size = sizeof(BitBandState),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("base", BitBandState, base, 0),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void armv7m_register_devices(void)
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{
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sysbus_register_withprop(&bitband_info);
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}
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device_init(armv7m_register_devices)
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