2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
727 lines
20 KiB
C
727 lines
20 KiB
C
/*
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* CFI parallel flash with Intel command set emulation
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*
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* Copyright (c) 2006 Thorsten Zitterell
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - CFI queries
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*
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* It does not support timings
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* It does not support flash interleaving
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*
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* It does not implement much more ...
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*/
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#include "hw.h"
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#include "flash.h"
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#include "block.h"
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#include "qemu-timer.h"
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#define PFLASH_BUG(fmt, ...) \
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do { \
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printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
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exit(1); \
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} while(0)
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/* #define PFLASH_DEBUG */
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, ...) \
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do { \
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printf("PFLASH: " fmt , ## __VA_ARGS__); \
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} while (0)
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#else
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#define DPRINTF(fmt, ...) do { } while (0)
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#endif
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struct pflash_t {
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BlockDriverState *bs;
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target_phys_addr_t base;
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target_phys_addr_t sector_len;
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target_phys_addr_t total_len;
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int width;
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int wcycle; /* if 0, the flash is read normally */
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int bypass;
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int ro;
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uint8_t cmd;
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uint8_t status;
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uint16_t ident[4];
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uint8_t cfi_len;
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uint8_t cfi_table[0x52];
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target_phys_addr_t counter;
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unsigned int writeblock_size;
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QEMUTimer *timer;
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ram_addr_t off;
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int fl_mem;
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void *storage;
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};
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static void pflash_timer (void *opaque)
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{
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pflash_t *pfl = opaque;
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */
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pfl->status ^= 0x80;
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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cpu_register_physical_memory(pfl->base, pfl->total_len,
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pfl->off | IO_MEM_ROMD | pfl->fl_mem);
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pfl->wcycle = 0;
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}
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pfl->cmd = 0;
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}
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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int width, int be)
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{
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target_phys_addr_t boff;
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uint32_t ret;
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uint8_t *p;
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ret = -1;
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boff = offset & 0xFF; /* why this here ?? */
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if (pfl->width == 2)
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boff = boff >> 1;
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else if (pfl->width == 4)
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boff = boff >> 2;
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#if 0
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DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
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__func__, offset, pfl->cmd, width);
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#endif
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switch (pfl->cmd) {
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case 0x00:
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/* Flash area read */
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p = pfl->storage;
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switch (width) {
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case 1:
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ret = p[offset];
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DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
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__func__, offset, ret);
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break;
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case 2:
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if (be) {
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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}
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DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
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__func__, offset, ret);
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break;
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case 4:
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if (be) {
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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}
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DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
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__func__, offset, ret);
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break;
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default:
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DPRINTF("BUG in %s\n", __func__);
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}
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break;
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case 0x20: /* Block erase */
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case 0x50: /* Clear status register */
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case 0x60: /* Block /un)lock */
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case 0x70: /* Status Register */
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case 0xe8: /* Write block */
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/* Status register read */
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ret = pfl->status;
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DPRINTF("%s: status %x\n", __func__, ret);
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break;
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case 0x90:
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switch (boff) {
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case 0:
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ret = pfl->ident[0] << 8 | pfl->ident[1];
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DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
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break;
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case 1:
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ret = pfl->ident[2] << 8 | pfl->ident[3];
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DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
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break;
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default:
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DPRINTF("%s: Read Device Information boff=%x\n", __func__, boff);
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ret = 0;
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break;
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}
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break;
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case 0x98: /* Query mode */
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if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff];
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break;
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default:
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/* This should never happen : reset state & treat it as a read */
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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}
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return ret;
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}
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset,
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int size)
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{
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int offset_end;
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if (pfl->bs) {
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offset_end = offset + size;
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/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9;
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bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset);
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}
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}
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static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
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uint32_t value, int width, int be)
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{
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uint8_t *p = pfl->storage;
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DPRINTF("%s: block write offset " TARGET_FMT_plx
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" value %x counter " TARGET_FMT_plx "\n",
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__func__, offset, value, pfl->counter);
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switch (width) {
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case 1:
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p[offset] = value;
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break;
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case 2:
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if (be) {
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p[offset] = value >> 8;
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p[offset + 1] = value;
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} else {
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p[offset] = value;
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p[offset + 1] = value >> 8;
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}
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break;
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case 4:
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if (be) {
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p[offset] = value >> 24;
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p[offset + 1] = value >> 16;
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p[offset + 2] = value >> 8;
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p[offset + 3] = value;
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} else {
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p[offset] = value;
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p[offset + 1] = value >> 8;
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p[offset + 2] = value >> 16;
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p[offset + 3] = value >> 24;
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}
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break;
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}
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}
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static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
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uint32_t value, int width, int be)
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{
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uint8_t *p;
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uint8_t cmd;
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cmd = value;
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DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
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__func__, offset, value, width, pfl->wcycle);
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if (!pfl->wcycle) {
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/* Set the device in I/O access mode */
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cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
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}
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switch (pfl->wcycle) {
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case 0:
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/* read mode */
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switch (cmd) {
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case 0x00: /* ??? */
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goto reset_flash;
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case 0x10: /* Single Byte Program */
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case 0x40: /* Single Byte Program */
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DPRINTF("%s: Single Byte Program\n", __func__);
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break;
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case 0x20: /* Block erase */
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p = pfl->storage;
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offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes "
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TARGET_FMT_plx "\n",
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__func__, offset, pfl->sector_len);
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memset(p + offset, 0xff, pfl->sector_len);
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pflash_update(pfl, offset, pfl->sector_len);
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pfl->status |= 0x80; /* Ready! */
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break;
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case 0x50: /* Clear status bits */
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DPRINTF("%s: Clear status bits\n", __func__);
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pfl->status = 0x0;
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goto reset_flash;
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case 0x60: /* Block (un)lock */
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DPRINTF("%s: Block unlock\n", __func__);
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break;
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case 0x70: /* Status Register */
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DPRINTF("%s: Read status register\n", __func__);
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pfl->cmd = cmd;
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return;
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case 0x90: /* Read Device ID */
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DPRINTF("%s: Read Device information\n", __func__);
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pfl->cmd = cmd;
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return;
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case 0x98: /* CFI query */
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DPRINTF("%s: CFI query\n", __func__);
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break;
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case 0xe8: /* Write to buffer */
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DPRINTF("%s: Write to buffer\n", __func__);
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pfl->status |= 0x80; /* Ready! */
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break;
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case 0xff: /* Read array mode */
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DPRINTF("%s: Read array mode\n", __func__);
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goto reset_flash;
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default:
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goto error_flash;
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}
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pfl->wcycle++;
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pfl->cmd = cmd;
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return;
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case 1:
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switch (pfl->cmd) {
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case 0x10: /* Single Byte Program */
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case 0x40: /* Single Byte Program */
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DPRINTF("%s: Single Byte Program\n", __func__);
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pflash_data_write(pfl, offset, value, width, be);
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pflash_update(pfl, offset, width);
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pfl->status |= 0x80; /* Ready! */
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pfl->wcycle = 0;
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break;
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case 0x20: /* Block erase */
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case 0x28:
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if (cmd == 0xd0) { /* confirm */
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pfl->wcycle = 0;
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pfl->status |= 0x80;
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} else if (cmd == 0xff) { /* read array mode */
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goto reset_flash;
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} else
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goto error_flash;
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break;
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case 0xe8:
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DPRINTF("%s: block write of %x bytes\n", __func__, value);
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pfl->counter = value;
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pfl->wcycle++;
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break;
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case 0x60:
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if (cmd == 0xd0) {
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pfl->wcycle = 0;
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pfl->status |= 0x80;
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} else if (cmd == 0x01) {
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pfl->wcycle = 0;
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pfl->status |= 0x80;
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} else if (cmd == 0xff) {
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goto reset_flash;
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} else {
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DPRINTF("%s: Unknown (un)locking command\n", __func__);
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goto reset_flash;
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}
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break;
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case 0x98:
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if (cmd == 0xff) {
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goto reset_flash;
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} else {
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DPRINTF("%s: leaving query mode\n", __func__);
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}
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break;
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default:
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goto error_flash;
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}
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return;
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case 2:
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switch (pfl->cmd) {
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case 0xe8: /* Block write */
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pflash_data_write(pfl, offset, value, width, be);
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pfl->status |= 0x80;
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if (!pfl->counter) {
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target_phys_addr_t mask = pfl->writeblock_size - 1;
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mask = ~mask;
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DPRINTF("%s: block write finished\n", __func__);
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pfl->wcycle++;
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/* Flush the entire write buffer onto backing storage. */
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pflash_update(pfl, offset & mask, pfl->writeblock_size);
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}
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pfl->counter--;
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break;
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default:
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goto error_flash;
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}
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return;
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case 3: /* Confirm mode */
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switch (pfl->cmd) {
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case 0xe8: /* Block write */
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if (cmd == 0xd0) {
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pfl->wcycle = 0;
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pfl->status |= 0x80;
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} else {
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DPRINTF("%s: unknown command for \"write block\"\n", __func__);
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PFLASH_BUG("Write block confirm");
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goto reset_flash;
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}
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break;
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default:
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goto error_flash;
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}
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return;
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default:
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/* Should never happen */
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DPRINTF("%s: invalid write state\n", __func__);
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goto reset_flash;
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}
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return;
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error_flash:
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printf("%s: Unimplemented flash cmd sequence "
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"(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n",
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__func__, offset, pfl->wcycle, pfl->cmd, value);
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reset_flash:
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cpu_register_physical_memory(pfl->base, pfl->total_len,
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pfl->off | IO_MEM_ROMD | pfl->fl_mem);
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pfl->bypass = 0;
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pfl->wcycle = 0;
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pfl->cmd = 0;
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return;
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}
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static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
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{
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return pflash_read(opaque, addr, 1, 1);
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}
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static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
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{
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return pflash_read(opaque, addr, 1, 0);
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}
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static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 2, 1);
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}
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static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 2, 0);
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}
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static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 4, 1);
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}
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static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
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{
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pflash_t *pfl = opaque;
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return pflash_read(pfl, addr, 4, 0);
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}
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static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1, 1);
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}
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static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_write(opaque, addr, value, 1, 0);
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}
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static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2, 1);
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}
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static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 2, 0);
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}
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static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4, 1);
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}
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static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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pflash_t *pfl = opaque;
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pflash_write(pfl, addr, value, 4, 0);
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}
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static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
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&pflash_writeb_be,
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&pflash_writew_be,
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&pflash_writel_be,
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};
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static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
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&pflash_readb_be,
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&pflash_readw_be,
|
|
&pflash_readl_be,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
|
|
&pflash_writeb_le,
|
|
&pflash_writew_le,
|
|
&pflash_writel_le,
|
|
};
|
|
|
|
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
|
|
&pflash_readb_le,
|
|
&pflash_readw_le,
|
|
&pflash_readl_le,
|
|
};
|
|
|
|
/* Count trailing zeroes of a 32 bits quantity */
|
|
static int ctz32 (uint32_t n)
|
|
{
|
|
int ret;
|
|
|
|
ret = 0;
|
|
if (!(n & 0xFFFF)) {
|
|
ret += 16;
|
|
n = n >> 16;
|
|
}
|
|
if (!(n & 0xFF)) {
|
|
ret += 8;
|
|
n = n >> 8;
|
|
}
|
|
if (!(n & 0xF)) {
|
|
ret += 4;
|
|
n = n >> 4;
|
|
}
|
|
if (!(n & 0x3)) {
|
|
ret += 2;
|
|
n = n >> 2;
|
|
}
|
|
if (!(n & 0x1)) {
|
|
ret++;
|
|
#if 0 /* This is not necessary as n is never 0 */
|
|
n = n >> 1;
|
|
#endif
|
|
}
|
|
#if 0 /* This is not necessary as n is never 0 */
|
|
if (!n)
|
|
ret++;
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
|
|
BlockDriverState *bs, uint32_t sector_len,
|
|
int nb_blocs, int width,
|
|
uint16_t id0, uint16_t id1,
|
|
uint16_t id2, uint16_t id3,
|
|
int be)
|
|
{
|
|
pflash_t *pfl;
|
|
target_phys_addr_t total_len;
|
|
int ret;
|
|
|
|
total_len = sector_len * nb_blocs;
|
|
|
|
/* XXX: to be fixed */
|
|
#if 0
|
|
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
|
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
|
return NULL;
|
|
#endif
|
|
|
|
pfl = qemu_mallocz(sizeof(pflash_t));
|
|
|
|
/* FIXME: Allocate ram ourselves. */
|
|
pfl->storage = qemu_get_ram_ptr(off);
|
|
if (be) {
|
|
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
|
|
pflash_write_ops_be, pfl,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
} else {
|
|
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
|
|
pflash_write_ops_le, pfl,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
}
|
|
pfl->off = off;
|
|
cpu_register_physical_memory(base, total_len,
|
|
off | pfl->fl_mem | IO_MEM_ROMD);
|
|
|
|
pfl->bs = bs;
|
|
if (pfl->bs) {
|
|
/* read the initial flash content */
|
|
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
|
|
if (ret < 0) {
|
|
cpu_unregister_io_memory(pfl->fl_mem);
|
|
qemu_free(pfl);
|
|
return NULL;
|
|
}
|
|
}
|
|
#if 0 /* XXX: there should be a bit to set up read-only,
|
|
* the same way the hardware does (with WP pin).
|
|
*/
|
|
pfl->ro = 1;
|
|
#else
|
|
pfl->ro = 0;
|
|
#endif
|
|
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
|
|
pfl->base = base;
|
|
pfl->sector_len = sector_len;
|
|
pfl->total_len = total_len;
|
|
pfl->width = width;
|
|
pfl->wcycle = 0;
|
|
pfl->cmd = 0;
|
|
pfl->status = 0;
|
|
pfl->ident[0] = id0;
|
|
pfl->ident[1] = id1;
|
|
pfl->ident[2] = id2;
|
|
pfl->ident[3] = id3;
|
|
/* Hardcoded CFI table */
|
|
pfl->cfi_len = 0x52;
|
|
/* Standard "QRY" string */
|
|
pfl->cfi_table[0x10] = 'Q';
|
|
pfl->cfi_table[0x11] = 'R';
|
|
pfl->cfi_table[0x12] = 'Y';
|
|
/* Command set (Intel) */
|
|
pfl->cfi_table[0x13] = 0x01;
|
|
pfl->cfi_table[0x14] = 0x00;
|
|
/* Primary extended table address (none) */
|
|
pfl->cfi_table[0x15] = 0x31;
|
|
pfl->cfi_table[0x16] = 0x00;
|
|
/* Alternate command set (none) */
|
|
pfl->cfi_table[0x17] = 0x00;
|
|
pfl->cfi_table[0x18] = 0x00;
|
|
/* Alternate extended table (none) */
|
|
pfl->cfi_table[0x19] = 0x00;
|
|
pfl->cfi_table[0x1A] = 0x00;
|
|
/* Vcc min */
|
|
pfl->cfi_table[0x1B] = 0x45;
|
|
/* Vcc max */
|
|
pfl->cfi_table[0x1C] = 0x55;
|
|
/* Vpp min (no Vpp pin) */
|
|
pfl->cfi_table[0x1D] = 0x00;
|
|
/* Vpp max (no Vpp pin) */
|
|
pfl->cfi_table[0x1E] = 0x00;
|
|
/* Reserved */
|
|
pfl->cfi_table[0x1F] = 0x07;
|
|
/* Timeout for min size buffer write */
|
|
pfl->cfi_table[0x20] = 0x07;
|
|
/* Typical timeout for block erase */
|
|
pfl->cfi_table[0x21] = 0x0a;
|
|
/* Typical timeout for full chip erase (4096 ms) */
|
|
pfl->cfi_table[0x22] = 0x00;
|
|
/* Reserved */
|
|
pfl->cfi_table[0x23] = 0x04;
|
|
/* Max timeout for buffer write */
|
|
pfl->cfi_table[0x24] = 0x04;
|
|
/* Max timeout for block erase */
|
|
pfl->cfi_table[0x25] = 0x04;
|
|
/* Max timeout for chip erase */
|
|
pfl->cfi_table[0x26] = 0x00;
|
|
/* Device size */
|
|
pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
|
|
/* Flash device interface (8 & 16 bits) */
|
|
pfl->cfi_table[0x28] = 0x02;
|
|
pfl->cfi_table[0x29] = 0x00;
|
|
/* Max number of bytes in multi-bytes write */
|
|
if (width == 1) {
|
|
pfl->cfi_table[0x2A] = 0x08;
|
|
} else {
|
|
pfl->cfi_table[0x2A] = 0x0B;
|
|
}
|
|
pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
|
|
|
|
pfl->cfi_table[0x2B] = 0x00;
|
|
/* Number of erase block regions (uniform) */
|
|
pfl->cfi_table[0x2C] = 0x01;
|
|
/* Erase block region 1 */
|
|
pfl->cfi_table[0x2D] = nb_blocs - 1;
|
|
pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
|
|
pfl->cfi_table[0x2F] = sector_len >> 8;
|
|
pfl->cfi_table[0x30] = sector_len >> 16;
|
|
|
|
/* Extended */
|
|
pfl->cfi_table[0x31] = 'P';
|
|
pfl->cfi_table[0x32] = 'R';
|
|
pfl->cfi_table[0x33] = 'I';
|
|
|
|
pfl->cfi_table[0x34] = '1';
|
|
pfl->cfi_table[0x35] = '1';
|
|
|
|
pfl->cfi_table[0x36] = 0x00;
|
|
pfl->cfi_table[0x37] = 0x00;
|
|
pfl->cfi_table[0x38] = 0x00;
|
|
pfl->cfi_table[0x39] = 0x00;
|
|
|
|
pfl->cfi_table[0x3a] = 0x00;
|
|
|
|
pfl->cfi_table[0x3b] = 0x00;
|
|
pfl->cfi_table[0x3c] = 0x00;
|
|
|
|
return pfl;
|
|
}
|