8d05ea8a33
Use ptimers for Sparc32 Slavio git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2859 c046a42c-6fe2-441c-8c8c-71466251a162
192 lines
4.4 KiB
C
192 lines
4.4 KiB
C
/*
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* General purpose implementation of a simple periodic countdown timer.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GNU LGPL.
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*/
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#include "vl.h"
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struct ptimer_state
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{
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int enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */
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uint64_t limit;
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uint64_t delta;
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uint32_t period_frac;
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int64_t period;
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int64_t last_event;
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int64_t next_event;
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QEMUBH *bh;
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QEMUTimer *timer;
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};
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/* Use a bottom-half routine to avoid reentrancy issues. */
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static void ptimer_trigger(ptimer_state *s)
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{
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if (s->bh) {
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qemu_bh_schedule(s->bh);
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}
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}
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static void ptimer_reload(ptimer_state *s)
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{
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if (s->delta == 0) {
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ptimer_trigger(s);
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s->delta = s->limit;
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}
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if (s->delta == 0 || s->period == 0) {
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fprintf(stderr, "Timer with period zero, disabling\n");
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s->enabled = 0;
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return;
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}
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s->last_event = s->next_event;
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s->next_event = s->last_event + s->delta * s->period;
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if (s->period_frac) {
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s->next_event += ((int64_t)s->period_frac * s->delta) >> 32;
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}
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qemu_mod_timer(s->timer, s->next_event);
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}
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static void ptimer_tick(void *opaque)
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{
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ptimer_state *s = (ptimer_state *)opaque;
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ptimer_trigger(s);
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s->delta = 0;
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if (s->enabled == 2) {
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s->enabled = 0;
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} else {
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ptimer_reload(s);
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}
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}
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uint64_t ptimer_get_count(ptimer_state *s)
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{
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int64_t now;
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uint64_t counter;
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if (s->enabled) {
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now = qemu_get_clock(vm_clock);
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/* Figure out the current counter value. */
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if (now - s->next_event > 0
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|| s->period == 0) {
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/* Prevent timer underflowing if it should already have
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triggered. */
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counter = 0;
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} else {
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uint64_t rem;
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uint64_t div;
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rem = s->next_event - now;
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div = s->period;
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counter = rem / div;
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}
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} else {
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counter = s->delta;
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}
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return counter;
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}
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void ptimer_set_count(ptimer_state *s, uint64_t count)
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{
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s->delta = count;
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if (s->enabled) {
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s->next_event = qemu_get_clock(vm_clock);
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ptimer_reload(s);
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}
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}
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void ptimer_run(ptimer_state *s, int oneshot)
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{
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if (s->period == 0) {
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fprintf(stderr, "Timer with period zero, disabling\n");
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return;
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}
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s->enabled = oneshot ? 2 : 1;
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s->next_event = qemu_get_clock(vm_clock);
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ptimer_reload(s);
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}
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/* Pause a timer. Note that this may cause it to "lose" time, even if it
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is immediately restarted. */
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void ptimer_stop(ptimer_state *s)
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{
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if (!s->enabled)
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return;
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s->delta = ptimer_get_count(s);
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qemu_del_timer(s->timer);
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s->enabled = 0;
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}
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/* Set counter increment interval in nanoseconds. */
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void ptimer_set_period(ptimer_state *s, int64_t period)
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{
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s->period = period;
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s->period_frac = 0;
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if (s->enabled) {
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s->next_event = qemu_get_clock(vm_clock);
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ptimer_reload(s);
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}
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}
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/* Set counter frequency in Hz. */
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void ptimer_set_freq(ptimer_state *s, uint32_t freq)
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{
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s->period = 1000000000ll / freq;
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s->period_frac = (1000000000ll << 32) / freq;
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if (s->enabled) {
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s->next_event = qemu_get_clock(vm_clock);
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ptimer_reload(s);
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}
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}
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/* Set the initial countdown value. If reload is nonzero then also set
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count = limit. */
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void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload)
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{
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s->limit = limit;
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if (reload)
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s->delta = limit;
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if (s->enabled) {
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s->next_event = qemu_get_clock(vm_clock);
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ptimer_reload(s);
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}
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}
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void qemu_put_ptimer(QEMUFile *f, ptimer_state *s)
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{
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qemu_put_byte(f, s->enabled);
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qemu_put_be64s(f, &s->limit);
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qemu_put_be64s(f, &s->delta);
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qemu_put_be32s(f, &s->period_frac);
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qemu_put_be64s(f, &s->period);
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qemu_put_be64s(f, &s->last_event);
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qemu_put_be64s(f, &s->next_event);
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qemu_put_timer(f, s->timer);
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}
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void qemu_get_ptimer(QEMUFile *f, ptimer_state *s)
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{
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s->enabled = qemu_get_byte(f);
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qemu_get_be64s(f, &s->limit);
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qemu_get_be64s(f, &s->delta);
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qemu_get_be32s(f, &s->period_frac);
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qemu_get_be64s(f, &s->period);
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qemu_get_be64s(f, &s->last_event);
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qemu_get_be64s(f, &s->next_event);
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qemu_get_timer(f, s->timer);
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}
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ptimer_state *ptimer_init(QEMUBH *bh)
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{
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ptimer_state *s;
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s = (ptimer_state *)qemu_mallocz(sizeof(ptimer_state));
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s->bh = bh;
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s->timer = qemu_new_timer(vm_clock, ptimer_tick, s);
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return s;
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}
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