244b1e81f6
Add an bswap16 and bswap32 ops, either using the rev and rev16 instructions on ARMv6+ or shifts and logical operations on previous ARM versions. In both cases the result use less instructions than the pure TCG version. These ops are also needed by the qemu_ld/st functions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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* Copyright (c) 2008 Andrzej Zaborowski
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_TARGET_ARM 1
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#define TCG_TARGET_REG_BITS 32
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#undef TCG_TARGET_WORDS_BIGENDIAN
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#undef TCG_TARGET_STACK_GROWSUP
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enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_PC,
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};
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#define TCG_TARGET_NB_REGS 16
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#define TCG_CT_CONST_ARM 0x100
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_R13
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#define TCG_TARGET_STACK_ALIGN 8
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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/* optional instructions */
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#define TCG_TARGET_HAS_ext8s_i32
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#define TCG_TARGET_HAS_ext16s_i32
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#undef TCG_TARGET_HAS_ext8u_i32 /* and r0, r1, #0xff */
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#define TCG_TARGET_HAS_ext16u_i32
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#define TCG_TARGET_HAS_bswap16_i32
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#define TCG_TARGET_HAS_bswap32_i32
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#define TCG_TARGET_HAS_not_i32
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#define TCG_TARGET_HAS_neg_i32
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#define TCG_TARGET_HAS_rot_i32
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#define TCG_TARGET_HAS_andc_i32
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// #define TCG_TARGET_HAS_orc_i32
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// #define TCG_TARGET_HAS_eqv_i32
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// #define TCG_TARGET_HAS_nand_i32
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// #define TCG_TARGET_HAS_nor_i32
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#define TCG_TARGET_HAS_GUEST_BASE
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enum {
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/* Note: must be synced with dyngen-exec.h */
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TCG_AREG0 = TCG_REG_R7,
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};
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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#if QEMU_GNUC_PREREQ(4, 1)
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__builtin___clear_cache((char *) start, (char *) stop);
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#else
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register unsigned long _beg __asm ("a1") = start;
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register unsigned long _end __asm ("a2") = stop;
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register unsigned long _flg __asm ("a3") = 0;
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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#endif
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}
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