ceffd34e85
In the CRIS v17 CPU an ADDC (add with carry) instruction has been added compared to the v10 instruction set. Assembler syntax: ADDC [Rs],Rd ADDC [Rs+],Rd Size: Dword Description: The source data is added together with the carry flag to the destination register. The size of the operation is dword. Operation: Rd += s + C-flag; Flags affected: S R P U I X N Z V C - - - - - 0 * * * * Instruction format: ADDC [Rs],Rd +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Instruction format: ADDC [Rs+],Rd +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ [EI: Shorten 80+ lines] Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Rabin Vincent <rabinv@axis.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/*
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* CRISv10 insn decoding macros.
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*
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* Copyright (c) 2010 AXIS Communications AB
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* Written by Edgar E. Iglesias.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define CRISV10_MODE_QIMMEDIATE 0
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#define CRISV10_MODE_REG 1
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#define CRISV10_MODE_INDIRECT 2
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#define CRISV10_MODE_AUTOINC 3
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/* Quick Immediate. */
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#define CRISV10_QIMM_BCC_R0 0
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#define CRISV10_QIMM_BCC_R1 1
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#define CRISV10_QIMM_BCC_R2 2
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#define CRISV10_QIMM_BCC_R3 3
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#define CRISV10_QIMM_BDAP_R0 4
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#define CRISV10_QIMM_BDAP_R1 5
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#define CRISV10_QIMM_BDAP_R2 6
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#define CRISV10_QIMM_BDAP_R3 7
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#define CRISV10_QIMM_ADDQ 8
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#define CRISV10_QIMM_MOVEQ 9
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#define CRISV10_QIMM_SUBQ 10
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#define CRISV10_QIMM_CMPQ 11
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#define CRISV10_QIMM_ANDQ 12
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#define CRISV10_QIMM_ORQ 13
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#define CRISV10_QIMM_ASHQ 14
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#define CRISV10_QIMM_LSHQ 15
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#define CRISV10_REG_ADDX 0
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#define CRISV10_REG_MOVX 1
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#define CRISV10_REG_SUBX 2
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#define CRISV10_REG_LSL 3
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#define CRISV10_REG_ADDI 4
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#define CRISV10_REG_BIAP 5
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#define CRISV10_REG_NEG 6
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#define CRISV10_REG_BOUND 7
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#define CRISV10_REG_ADD 8
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#define CRISV10_REG_MOVE_R 9
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#define CRISV10_REG_MOVE_SPR_R 9
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#define CRISV10_REG_MOVE_R_SPR 8
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#define CRISV10_REG_SUB 10
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#define CRISV10_REG_CMP 11
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#define CRISV10_REG_AND 12
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#define CRISV10_REG_OR 13
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#define CRISV10_REG_ASR 14
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#define CRISV10_REG_LSR 15
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#define CRISV10_REG_BTST 3
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#define CRISV10_REG_SCC 4
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#define CRISV10_REG_SETF 6
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#define CRISV10_REG_CLEARF 7
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#define CRISV10_REG_BIAP 5
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#define CRISV10_REG_ABS 10
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#define CRISV10_REG_DSTEP 11
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#define CRISV10_REG_LZ 12
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#define CRISV10_REG_NOT 13
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#define CRISV10_REG_SWAP 13
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#define CRISV10_REG_XOR 14
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#define CRISV10_REG_MSTEP 15
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/* Indirect, var size. */
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#define CRISV10_IND_TEST 14
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#define CRISV10_IND_MUL 4
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#define CRISV10_IND_BDAP_M 5
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#define CRISV10_IND_ADD 8
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#define CRISV10_IND_MOVE_M_R 9
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/* indirect fixed size. */
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#define CRISV10_IND_ADDX 0
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#define CRISV10_IND_MOVX 1
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#define CRISV10_IND_SUBX 2
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#define CRISV10_IND_CMPX 3
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#define CRISV10_IND_JUMP_M 4
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#define CRISV10_IND_DIP 5
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#define CRISV10_IND_JUMP_R 6
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#define CRISV17_IND_ADDC 6
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#define CRISV10_IND_BOUND 7
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#define CRISV10_IND_BCC_M 7
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#define CRISV10_IND_MOVE_M_SPR 8
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#define CRISV10_IND_MOVE_SPR_M 9
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#define CRISV10_IND_SUB 10
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#define CRISV10_IND_CMP 11
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#define CRISV10_IND_AND 12
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#define CRISV10_IND_OR 13
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#define CRISV10_IND_MOVE_R_M 15
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#define CRISV10_IND_MOVEM_M_R 14
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#define CRISV10_IND_MOVEM_R_M 15
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