299 lines
7.0 KiB
C
299 lines
7.0 KiB
C
/*
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* libqos PCI bindings for PC
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "libqtest.h"
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#include "libqos/pci-pc.h"
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#include "hw/pci/pci_regs.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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#include <glib.h>
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#define ACPI_PCIHP_ADDR 0xae00
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#define PCI_EJ_BASE 0x0008
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typedef struct QPCIBusPC
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{
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QPCIBus bus;
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uint32_t pci_hole_start;
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uint32_t pci_hole_size;
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uint32_t pci_hole_alloc;
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uint16_t pci_iohole_start;
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uint16_t pci_iohole_size;
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uint16_t pci_iohole_alloc;
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} QPCIBusPC;
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static uint8_t qpci_pc_io_readb(QPCIBus *bus, void *addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint8_t value;
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if (port < 0x10000) {
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value = inb(port);
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} else {
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value = readb(port);
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}
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return value;
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}
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static uint16_t qpci_pc_io_readw(QPCIBus *bus, void *addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint16_t value;
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if (port < 0x10000) {
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value = inw(port);
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} else {
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value = readw(port);
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}
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return value;
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}
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static uint32_t qpci_pc_io_readl(QPCIBus *bus, void *addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint32_t value;
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if (port < 0x10000) {
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value = inl(port);
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} else {
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value = readl(port);
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}
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return value;
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}
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static void qpci_pc_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outb(port, value);
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} else {
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writeb(port, value);
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}
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}
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static void qpci_pc_io_writew(QPCIBus *bus, void *addr, uint16_t value)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outw(port, value);
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} else {
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writew(port, value);
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}
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}
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static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outl(port, value);
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} else {
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writel(port, value);
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}
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}
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static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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return inb(0xcfc);
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}
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static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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return inw(0xcfc);
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}
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static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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return inl(0xcfc);
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}
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static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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outb(0xcfc, value);
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}
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static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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outw(0xcfc, value);
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}
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static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
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{
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outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
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outl(0xcfc, value);
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}
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static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno, uint64_t *sizeptr)
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{
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QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
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static const int bar_reg_map[] = {
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PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
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PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
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};
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int bar_reg;
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uint32_t addr;
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uint64_t size;
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uint32_t io_type;
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g_assert(barno >= 0 && barno <= 5);
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bar_reg = bar_reg_map[barno];
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qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
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addr = qpci_config_readl(dev, bar_reg);
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io_type = addr & PCI_BASE_ADDRESS_SPACE;
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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addr &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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addr &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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size = (1ULL << ctzl(addr));
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if (size == 0) {
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return NULL;
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}
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if (sizeptr) {
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*sizeptr = size;
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}
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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uint16_t loc;
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g_assert((s->pci_iohole_alloc + size) <= s->pci_iohole_size);
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loc = s->pci_iohole_start + s->pci_iohole_alloc;
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s->pci_iohole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
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return (void *)(intptr_t)loc;
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} else {
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uint64_t loc;
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g_assert((s->pci_hole_alloc + size) <= s->pci_hole_size);
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loc = s->pci_hole_start + s->pci_hole_alloc;
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s->pci_hole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc);
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return (void *)(intptr_t)loc;
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}
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}
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static void qpci_pc_iounmap(QPCIBus *bus, void *data)
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{
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/* FIXME */
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}
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QPCIBus *qpci_init_pc(void)
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{
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QPCIBusPC *ret;
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ret = g_malloc(sizeof(*ret));
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ret->bus.io_readb = qpci_pc_io_readb;
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ret->bus.io_readw = qpci_pc_io_readw;
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ret->bus.io_readl = qpci_pc_io_readl;
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ret->bus.io_writeb = qpci_pc_io_writeb;
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ret->bus.io_writew = qpci_pc_io_writew;
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ret->bus.io_writel = qpci_pc_io_writel;
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ret->bus.config_readb = qpci_pc_config_readb;
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ret->bus.config_readw = qpci_pc_config_readw;
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ret->bus.config_readl = qpci_pc_config_readl;
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ret->bus.config_writeb = qpci_pc_config_writeb;
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ret->bus.config_writew = qpci_pc_config_writew;
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ret->bus.config_writel = qpci_pc_config_writel;
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ret->bus.iomap = qpci_pc_iomap;
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ret->bus.iounmap = qpci_pc_iounmap;
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ret->pci_hole_start = 0xE0000000;
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ret->pci_hole_size = 0x20000000;
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ret->pci_hole_alloc = 0;
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ret->pci_iohole_start = 0xc000;
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ret->pci_iohole_size = 0x4000;
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ret->pci_iohole_alloc = 0;
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return &ret->bus;
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}
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void qpci_free_pc(QPCIBus *bus)
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{
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QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
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g_free(s);
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}
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void qpci_plug_device_test(const char *driver, const char *id,
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uint8_t slot, const char *opts)
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{
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QDict *response;
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char *cmd;
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cmd = g_strdup_printf("{'execute': 'device_add',"
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" 'arguments': {"
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" 'driver': '%s',"
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" 'addr': '%d',"
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" %s%s"
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" 'id': '%s'"
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"}}", driver, slot,
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opts ? opts : "", opts ? "," : "",
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id);
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response = qmp(cmd);
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g_free(cmd);
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g_assert(response);
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g_assert(!qdict_haskey(response, "error"));
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QDECREF(response);
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}
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void qpci_unplug_acpi_device_test(const char *id, uint8_t slot)
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{
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QDict *response;
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char *cmd;
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cmd = g_strdup_printf("{'execute': 'device_del',"
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" 'arguments': {"
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" 'id': '%s'"
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"}}", id);
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response = qmp(cmd);
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g_free(cmd);
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g_assert(response);
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g_assert(!qdict_haskey(response, "error"));
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QDECREF(response);
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outb(ACPI_PCIHP_ADDR + PCI_EJ_BASE, 1 << slot);
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response = qmp("");
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g_assert(response);
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g_assert(qdict_haskey(response, "event"));
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g_assert(!strcmp(qdict_get_str(response, "event"), "DEVICE_DELETED"));
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QDECREF(response);
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}
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