386 lines
12 KiB
C
386 lines
12 KiB
C
/*
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* QEMU PowerPC PowerNV (POWER9) PHB4 model
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*
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* Copyright (c) 2018-2020, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/fdt.h"
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#include "hw/pci-host/pnv_phb4_regs.h"
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#include "hw/pci-host/pnv_phb4.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_chip.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/sysemu.h"
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#include <libfdt.h>
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#define phb_pec_error(pec, fmt, ...) \
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qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \
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(pec)->chip_id, (pec)->index, ## __VA_ARGS__)
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static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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/* TODO: add list of allowed registers and error out if not */
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return pec->nest_regs[reg];
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}
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static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PEC_NEST_PBCQ_HW_CONFIG:
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case PEC_NEST_DROP_PRIO_CTRL:
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case PEC_NEST_PBCQ_ERR_INJECT:
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case PEC_NEST_PCI_NEST_CLK_TRACE_CTL:
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case PEC_NEST_PBCQ_PMON_CTRL:
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case PEC_NEST_PBCQ_PBUS_ADDR_EXT:
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case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT:
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case PEC_NEST_CAPP_CTRL:
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case PEC_NEST_PBCQ_READ_STK_OVR:
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case PEC_NEST_PBCQ_WRITE_STK_OVR:
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case PEC_NEST_PBCQ_STORE_STK_OVR:
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case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL:
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pec->nest_regs[reg] = val;
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break;
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default:
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phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
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addr, val);
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}
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}
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static const MemoryRegionOps pnv_pec_nest_xscom_ops = {
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.read = pnv_pec_nest_xscom_read,
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.write = pnv_pec_nest_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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/* TODO: add list of allowed registers and error out if not */
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return pec->pci_regs[reg];
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}
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static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PEC_PCI_PBAIB_HW_CONFIG:
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case PEC_PCI_PBAIB_READ_STK_OVR:
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pec->pci_regs[reg] = val;
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break;
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default:
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phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
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addr, val);
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}
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}
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static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
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.read = pnv_pec_pci_xscom_read,
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.write = pnv_pec_pci_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
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{
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PnvPhb4PecState *pecs = NULL;
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int chip_id = phb->chip_id;
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int index = phb->phb_id;
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int i, j;
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if (phb->version == 4) {
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Pnv9Chip *chip9 = PNV9_CHIP(chip);
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pecs = chip9->pecs;
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} else if (phb->version == 5) {
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Pnv10Chip *chip10 = PNV10_CHIP(chip);
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pecs = chip10->pecs;
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} else {
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g_assert_not_reached();
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}
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for (i = 0; i < chip->num_pecs; i++) {
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/*
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* For each PEC, check the amount of phbs it supports
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* and see if the given phb4 index matches an index.
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*/
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PnvPhb4PecState *pec = &pecs[i];
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for (j = 0; j < pec->num_phbs; j++) {
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if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
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pec->phbs[j] = phb;
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phb->pec = pec;
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return pec;
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}
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}
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}
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error_setg(errp,
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"pnv-phb4 chip-id %d index %d didn't match any existing PEC",
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chip_id, index);
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return NULL;
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}
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static PnvPHB *pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
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int stack_no,
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Error **errp)
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{
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PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB));
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int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
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object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));
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object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
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&error_abort);
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object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id,
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&error_fatal);
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object_property_set_int(OBJECT(phb), "index", phb_id,
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&error_fatal);
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if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
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return NULL;
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}
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return phb;
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}
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static void pnv_pec_realize(DeviceState *dev, Error **errp)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
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char name[64];
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int i;
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if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
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error_setg(errp, "invalid PEC index: %d", pec->index);
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return;
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}
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pec->num_phbs = pecc->num_phbs[pec->index];
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/* Create PHBs if running with defaults */
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if (defaults_enabled()) {
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g_assert(pec->num_phbs <= MAX_PHBS_PER_PEC);
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for (i = 0; i < pec->num_phbs; i++) {
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pec->phbs[i] = pnv_pec_default_phb_realize(pec, i, errp);
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}
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}
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/* Initialize the XSCOM regions for the PEC registers */
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snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
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pec->index);
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pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev),
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&pnv_pec_nest_xscom_ops, pec, name,
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PHB4_PEC_NEST_REGS_COUNT);
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snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id,
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pec->index);
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pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev),
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&pnv_pec_pci_xscom_ops, pec, name,
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PHB4_PEC_PCI_REGS_COUNT);
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}
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static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
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int xscom_offset)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev);
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uint32_t nbase = pecc->xscom_nest_base(pec);
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uint32_t pbase = pecc->xscom_pci_base(pec);
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int offset, i;
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char *name;
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uint32_t reg[] = {
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cpu_to_be32(nbase),
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cpu_to_be32(pecc->xscom_nest_size),
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cpu_to_be32(pbase),
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cpu_to_be32(pecc->xscom_pci_size),
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};
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name = g_strdup_printf("pbcq@%x", nbase);
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offset = fdt_add_subnode(fdt, xscom_offset, name);
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_FDT(offset);
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g_free(name);
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_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index)));
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_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1)));
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_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0)));
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_FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
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pecc->compat_size)));
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for (i = 0; i < pec->num_phbs; i++) {
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int stk_offset;
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if (!pec->phbs[i]) {
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continue;
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}
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name = g_strdup_printf("stack@%x", i);
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stk_offset = fdt_add_subnode(fdt, offset, name);
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_FDT(stk_offset);
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g_free(name);
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_FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat,
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pecc->stk_compat_size)));
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_FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i)));
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_FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index",
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pec->phbs[i]->phb_id)));
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}
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return 0;
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}
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static Property pnv_pec_properties[] = {
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DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
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DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
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DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
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PnvChip *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
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{
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return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
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}
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static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
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{
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return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index;
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}
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/*
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* PEC0 -> 1 phb
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* PEC1 -> 2 phb
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* PEC2 -> 3 phbs
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*/
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static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 };
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static void pnv_pec_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
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static const char compat[] = "ibm,power9-pbcq";
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static const char stk_compat[] = "ibm,power9-phb-stack";
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xdc->dt_xscom = pnv_pec_dt_xscom;
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dc->realize = pnv_pec_realize;
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device_class_set_props(dc, pnv_pec_properties);
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dc->user_creatable = false;
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pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
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pecc->xscom_pci_base = pnv_pec_xscom_pci_base;
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pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE;
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pecc->xscom_pci_size = PNV9_XSCOM_PEC_PCI_SIZE;
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pecc->compat = compat;
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pecc->compat_size = sizeof(compat);
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pecc->stk_compat = stk_compat;
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pecc->stk_compat_size = sizeof(stk_compat);
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pecc->version = PNV_PHB4_VERSION;
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pecc->phb_type = TYPE_PNV_PHB4;
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pecc->num_phbs = pnv_pec_num_phbs;
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}
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static const TypeInfo pnv_pec_type_info = {
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.name = TYPE_PNV_PHB4_PEC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvPhb4PecState),
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.class_init = pnv_pec_class_init,
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.class_size = sizeof(PnvPhb4PecClass),
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_PNV_XSCOM_INTERFACE },
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{ }
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}
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};
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/*
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* POWER10 definitions
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*/
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static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
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{
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return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
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}
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static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
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{
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/* index goes down ... */
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return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
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}
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/*
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* PEC0 -> 3 stacks
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* PEC1 -> 3 stacks
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*/
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static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
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static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
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{
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
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static const char compat[] = "ibm,power10-pbcq";
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static const char stk_compat[] = "ibm,power10-phb-stack";
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pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
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pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
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pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
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pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
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pecc->compat = compat;
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pecc->compat_size = sizeof(compat);
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pecc->stk_compat = stk_compat;
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pecc->stk_compat_size = sizeof(stk_compat);
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pecc->version = PNV_PHB5_VERSION;
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pecc->phb_type = TYPE_PNV_PHB5;
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pecc->num_phbs = pnv_phb5_pec_num_stacks;
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}
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static const TypeInfo pnv_phb5_pec_type_info = {
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.name = TYPE_PNV_PHB5_PEC,
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.parent = TYPE_PNV_PHB4_PEC,
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.instance_size = sizeof(PnvPhb4PecState),
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.class_init = pnv_phb5_pec_class_init,
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.class_size = sizeof(PnvPhb4PecClass),
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_PNV_XSCOM_INTERFACE },
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{ }
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}
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};
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static void pnv_pec_register_types(void)
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{
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type_register_static(&pnv_pec_type_info);
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type_register_static(&pnv_phb5_pec_type_info);
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}
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type_init(pnv_pec_register_types);
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