qemu-e2k/target-arm
Peter Maydell 2a0308c54f target-arm: Fix UNDEF cases in Thumb load/store
Decode of Thumb load/store was merging together the cases of 'bit 11==0'
(reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work for
valid instruction patterns but meant that we would not UNDEF for the
cases the architecture mandates that we must. Make the decode actually
look at bit 11 as well as [10..8] so that we UNDEF in the right places.

This change also removes what was a spurious unreachable 'case 8',
and correctly frees TCG temporaries on the illegal-insn codepaths.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22 07:52:35 +01:00
..
cpu.h target-arm: Implement cp15 VA->PA translation 2011-03-06 23:37:18 +01:00
exec.h inline cpu_halted into sole caller 2011-03-13 14:44:21 +00:00
helper.c target-arm: Implement cp15 VA->PA translation 2011-03-06 23:37:18 +01:00
helpers.h target-arm: Move Neon VZIP to helper functions 2011-02-20 17:31:53 +01:00
iwmmxt_helper.c Update to a hopefully more future proof FSF address 2009-07-16 20:47:01 +00:00
machine.c target-arm: Implement cp15 VA->PA translation 2011-03-06 23:37:18 +01:00
neon_helper.c target-arm: Fix unsigned VQRSHL by large shift counts 2011-02-20 17:43:01 +01:00
op_addsub.h target-arm: fix addsub/subadd implementation 2010-07-01 23:45:29 +02:00
op_helper.c Set the right overflow bit for neon 32 and 64 bit saturating add/sub. 2011-02-04 20:57:41 +01:00
translate.c target-arm: Fix UNDEF cases in Thumb load/store 2011-03-22 07:52:35 +01:00