674b0a5784
hw/pci/pci_bridge.h and hw/cxl/cxl.h include each other. Fortunately, breaking the loop is merely a matter of deleting unnecessary includes from headers, and adding them back in places where they are now missing. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-2-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
253 lines
9.5 KiB
C
253 lines
9.5 KiB
C
#ifndef HW_ICH9_H
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#define HW_ICH9_H
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#include "hw/isa/isa.h"
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#include "hw/sysbus.h"
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#include "hw/i386/pc.h"
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#include "hw/isa/apm.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/ich9.h"
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#include "qom/object.h"
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void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
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int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
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PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
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void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
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I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
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void ich9_generate_smi(void);
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#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
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#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
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OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE)
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struct ICH9LPCState {
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/* ICH9 LPC PCI to ISA bridge */
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PCIDevice d;
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/* (pci device, intx) -> pirq
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* In real chipset case, the unused slots are never used
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* as ICH9 supports only D25-D31 irq routing.
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* On the other hand in qemu case, any slot/function can be populated
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* via command line option.
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* So fallback interrupt routing for any devices in any slots is necessary.
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*/
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uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
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APMState apm;
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ICH9LPCPMRegs pm;
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uint32_t sci_level; /* track sci level */
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uint8_t sci_gsi;
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/* 2.24 Pin Straps */
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struct {
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bool spkr_hi;
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} pin_strap;
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/* 10.1 Chipset Configuration registers(Memory Space)
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which is pointed by RCBA */
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uint8_t chip_config[ICH9_CC_SIZE];
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/*
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* 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
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*
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* register contents and IO memory region
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*/
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uint8_t rst_cnt;
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MemoryRegion rst_cnt_mem;
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/* SMI feature negotiation via fw_cfg */
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uint64_t smi_host_features; /* guest-invisible, host endian */
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uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little
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* endian uint64_t */
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uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little
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* endian uint64_t */
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uint8_t smi_features_ok; /* guest-visible, read-only; selecting it
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* triggers feature lockdown */
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uint64_t smi_negotiated_features; /* guest-invisible, host endian */
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/* isa bus */
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ISABus *isa_bus;
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MemoryRegion rcrb_mem; /* root complex register block */
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Notifier machine_ready;
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qemu_irq gsi[GSI_NUM_PINS];
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};
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#define Q35_MASK(bit, ms_bit, ls_bit) \
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((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
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/* ICH9: Chipset Configuration Registers */
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#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
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#define ICH9_CC
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#define ICH9_CC_D28IP 0x310C
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#define ICH9_CC_D28IP_SHIFT 4
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#define ICH9_CC_D28IP_MASK 0xf
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#define ICH9_CC_D28IP_DEFAULT 0x00214321
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#define ICH9_CC_D31IR 0x3140
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#define ICH9_CC_D30IR 0x3142
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#define ICH9_CC_D29IR 0x3144
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#define ICH9_CC_D28IR 0x3146
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#define ICH9_CC_D27IR 0x3148
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#define ICH9_CC_D26IR 0x314C
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#define ICH9_CC_D25IR 0x3150
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#define ICH9_CC_DIR_DEFAULT 0x3210
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#define ICH9_CC_D30IR_DEFAULT 0x0
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#define ICH9_CC_DIR_SHIFT 4
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#define ICH9_CC_DIR_MASK 0x7
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#define ICH9_CC_OIC 0x31FF
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#define ICH9_CC_OIC_AEN 0x1
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#define ICH9_CC_GCS 0x3410
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#define ICH9_CC_GCS_DEFAULT 0x00000020
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#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
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/* D28:F[0-5] */
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#define ICH9_PCIE_DEV 28
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#define ICH9_PCIE_FUNC_MAX 6
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/* D29:F0 USB UHCI Controller #1 */
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#define ICH9_USB_UHCI1_DEV 29
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#define ICH9_USB_UHCI1_FUNC 0
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/* D30:F0 DMI-to-PCI bridge */
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#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
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#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
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#define ICH9_D2P_BRIDGE_DEV 30
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#define ICH9_D2P_BRIDGE_FUNC 0
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#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
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#define ICH9_D2P_A2_REVISION 0x92
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/* D31:F0 LPC Processor Interface */
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#define ICH9_RST_CNT_IOPORT 0xCF9
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/* D31:F1 LPC controller */
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#define ICH9_A2_LPC "ICH9 A2 LPC"
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#define ICH9_A2_LPC_SAVEVM_VERSION 0
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#define ICH9_LPC_DEV 31
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#define ICH9_LPC_FUNC 0
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#define ICH9_A2_LPC_REVISION 0x2
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#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
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#define ICH9_LPC_PMBASE 0x40
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#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
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#define ICH9_LPC_PMBASE_RTE 0x1
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#define ICH9_LPC_PMBASE_DEFAULT 0x1
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#define ICH9_LPC_ACPI_CTRL 0x44
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#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
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#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
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#define ICH9_LPC_ACPI_CTRL_9 0x0
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#define ICH9_LPC_ACPI_CTRL_10 0x1
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#define ICH9_LPC_ACPI_CTRL_11 0x2
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#define ICH9_LPC_ACPI_CTRL_20 0x4
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#define ICH9_LPC_ACPI_CTRL_21 0x5
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#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
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#define ICH9_LPC_PIRQA_ROUT 0x60
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#define ICH9_LPC_PIRQB_ROUT 0x61
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#define ICH9_LPC_PIRQC_ROUT 0x62
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#define ICH9_LPC_PIRQD_ROUT 0x63
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#define ICH9_LPC_PIRQE_ROUT 0x68
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#define ICH9_LPC_PIRQF_ROUT 0x69
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#define ICH9_LPC_PIRQG_ROUT 0x6a
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#define ICH9_LPC_PIRQH_ROUT 0x6b
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#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
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#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
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#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
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#define ICH9_LPC_GEN_PMCON_1 0xa0
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#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
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#define ICH9_LPC_GEN_PMCON_2 0xa2
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#define ICH9_LPC_GEN_PMCON_3 0xa4
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#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
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#define ICH9_LPC_RCBA 0xf0
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#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
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#define ICH9_LPC_RCBA_EN 0x1
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#define ICH9_LPC_RCBA_DEFAULT 0x0
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#define ICH9_LPC_PIC_NUM_PINS 16
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#define ICH9_LPC_IOAPIC_NUM_PINS 24
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#define ICH9_GPIO_GSI "gsi"
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/* D31:F2 SATA Controller #1 */
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#define ICH9_SATA1_DEV 31
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#define ICH9_SATA1_FUNC 2
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/* D31:F0 power management I/O registers
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offset from the address ICH9_LPC_PMBASE */
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/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
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#define ICH9_PMIO_SIZE 128
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#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
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#define ICH9_PMIO_PM1_STS 0x00
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#define ICH9_PMIO_PM1_EN 0x02
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#define ICH9_PMIO_PM1_CNT 0x04
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#define ICH9_PMIO_PM1_TMR 0x08
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#define ICH9_PMIO_GPE0_STS 0x20
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#define ICH9_PMIO_GPE0_EN 0x28
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#define ICH9_PMIO_GPE0_LEN 16
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#define ICH9_PMIO_SMI_EN 0x30
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#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
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#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
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#define ICH9_PMIO_SMI_STS 0x34
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#define ICH9_PMIO_TCO_RLD 0x60
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#define ICH9_PMIO_TCO_LEN 32
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/* FADT ACPI_ENABLE/ACPI_DISABLE */
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#define ICH9_APM_ACPI_ENABLE 0x2
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#define ICH9_APM_ACPI_DISABLE 0x3
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/* D31:F3 SMBus controller */
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#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB"
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#define ICH9_A2_SMB_REVISION 0x02
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#define ICH9_SMB_PI 0x00
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#define ICH9_SMB_SMBMBAR0 0x10
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#define ICH9_SMB_SMBMBAR1 0x14
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#define ICH9_SMB_SMBM_BAR 0
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#define ICH9_SMB_SMBM_SIZE (1 << 8)
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#define ICH9_SMB_SMB_BASE 0x20
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#define ICH9_SMB_SMB_BASE_BAR 4
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#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
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#define ICH9_SMB_HOSTC 0x40
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#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
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#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
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#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
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#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
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/* D31:F3 SMBus I/O and memory mapped I/O registers */
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#define ICH9_SMB_DEV 31
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#define ICH9_SMB_FUNC 3
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#define ICH9_SMB_HST_STS 0x00
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#define ICH9_SMB_HST_CNT 0x02
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#define ICH9_SMB_HST_CMD 0x03
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#define ICH9_SMB_XMIT_SLVA 0x04
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#define ICH9_SMB_HST_D0 0x05
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#define ICH9_SMB_HST_D1 0x06
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#define ICH9_SMB_HOST_BLOCK_DB 0x07
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#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features"
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/* bit positions used in fw_cfg SMI feature negotiation */
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#define ICH9_LPC_SMI_F_BROADCAST_BIT 0
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#define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1
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#define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2
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#endif /* HW_ICH9_H */
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