451 lines
12 KiB
C
451 lines
12 KiB
C
/*
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* sparc helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h"
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//#define DEBUG_PCALL
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//#define DEBUG_MMU
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/* Sparc MMU emulation */
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/* thread support */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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void cpu_lock(void)
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{
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spin_lock(&global_cpu_lock);
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}
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void cpu_unlock(void)
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{
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spin_unlock(&global_cpu_lock);
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}
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#if defined(CONFIG_USER_ONLY)
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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env->mmuregs[4] = address;
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if (rw & 2)
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env->exception_index = TT_TFAULT;
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else
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env->exception_index = TT_DFAULT;
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return 1;
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}
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#else
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#define MMUSUFFIX _mmu
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#define GETPC() (__builtin_return_address(0))
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
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{
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TranslationBlock *tb;
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int ret;
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unsigned long pc;
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CPUState *saved_env;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env;
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env = cpu_single_env;
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ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
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if (ret) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (unsigned long)retaddr;
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, (void *)T2);
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}
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}
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cpu_loop_exit();
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}
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env = saved_env;
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}
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static const int access_table[8][8] = {
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{ 0, 0, 0, 0, 2, 0, 3, 3 },
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{ 0, 0, 0, 0, 2, 0, 0, 0 },
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{ 2, 2, 0, 0, 0, 2, 3, 3 },
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{ 2, 2, 0, 0, 0, 2, 0, 0 },
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{ 2, 0, 2, 0, 2, 2, 3, 3 },
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{ 2, 0, 2, 0, 2, 0, 2, 0 },
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{ 2, 2, 2, 0, 2, 2, 3, 3 },
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{ 2, 2, 2, 0, 2, 2, 2, 0 }
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};
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/* 1 = write OK */
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static const int rw_table[2][8] = {
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{ 0, 1, 0, 1, 0, 1, 0, 1 },
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{ 0, 1, 0, 1, 0, 0, 0, 0 }
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};
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int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
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int *access_index, target_ulong address, int rw,
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int is_user)
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{
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int access_perms = 0;
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target_phys_addr_t pde_ptr;
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uint32_t pde;
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target_ulong virt_addr;
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int error_code = 0, is_dirty;
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unsigned long page_offset;
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virt_addr = address & TARGET_PAGE_MASK;
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return 0;
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}
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
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*physical = 0xfffff000;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
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pde = ldl_phys(pde_ptr);
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return 1 << 2;
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case 2: /* L0 PTE, maybe should not happen? */
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case 3: /* Reserved */
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return 4 << 2;
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case 1: /* L0 PDE */
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (1 << 8) | (1 << 2);
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case 3: /* Reserved */
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return (1 << 8) | (4 << 2);
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case 1: /* L1 PDE */
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (2 << 8) | (1 << 2);
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case 3: /* Reserved */
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return (2 << 8) | (4 << 2);
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case 1: /* L2 PDE */
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (3 << 8) | (1 << 2);
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case 1: /* PDE, should not happen */
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case 3: /* Reserved */
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return (3 << 8) | (4 << 2);
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case 2: /* L3 PTE */
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virt_addr = address & TARGET_PAGE_MASK;
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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}
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break;
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case 2: /* L2 PTE */
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
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}
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break;
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case 2: /* L1 PTE */
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
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}
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}
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK;
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if (is_dirty)
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pde |= PG_MODIFIED_MASK;
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stl_phys_notdirty(pde_ptr, pde);
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}
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
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error_code = access_table[*access_index][access_perms];
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if (error_code && !(env->mmuregs[0] & MMU_NF))
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return error_code;
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/* the page can be put in the TLB */
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*prot = PAGE_READ;
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if (pde & PG_MODIFIED_MASK) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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if (rw_table[is_user][access_perms])
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*prot |= PAGE_WRITE;
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}
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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}
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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target_ulong virt_addr;
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target_phys_addr_t paddr;
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unsigned long vaddr;
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int error_code = 0, prot, ret = 0, access_index;
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
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if (error_code == 0) {
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virt_addr = address & TARGET_PAGE_MASK;
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vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
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return ret;
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}
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if (env->mmuregs[3]) /* Fault status register */
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */
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env->mmuregs[3] |= (access_index << 5) | error_code | 2;
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env->mmuregs[4] = address; /* Fault address register */
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE;
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
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return ret;
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} else {
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if (rw & 2)
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env->exception_index = TT_TFAULT;
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else
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env->exception_index = TT_DFAULT;
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return 1;
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}
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}
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#endif
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void memcpy32(target_ulong *dst, const target_ulong *src)
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{
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dst[0] = src[0];
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dst[1] = src[1];
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dst[2] = src[2];
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dst[3] = src[3];
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dst[4] = src[4];
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dst[5] = src[5];
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dst[6] = src[6];
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dst[7] = src[7];
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}
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void set_cwp(int new_cwp)
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{
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/* put the modified wrap registers at their proper location */
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if (env->cwp == (NWINDOWS - 1))
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memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
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env->cwp = new_cwp;
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/* put the wrap registers at their temporary location */
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if (new_cwp == (NWINDOWS - 1))
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memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
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env->regwptr = env->regbase + (new_cwp * 16);
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}
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void cpu_set_cwp(CPUState *env1, int new_cwp)
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{
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CPUState *saved_env;
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saved_env = env;
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env = env1;
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set_cwp(new_cwp);
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env = saved_env;
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}
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void do_interrupt(int intno)
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{
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int cwp;
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#ifdef DEBUG_PCALL
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if (loglevel & CPU_LOG_INT) {
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static int count;
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fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
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count, intno,
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env->pc,
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env->npc, env->regwptr[6]);
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cpu_dump_state(env, logfile, fprintf, 0);
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#if 0
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{
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int i;
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uint8_t *ptr;
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fprintf(logfile, " code=");
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ptr = (uint8_t *)env->pc;
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for(i = 0; i < 16; i++) {
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fprintf(logfile, " %02x", ldub(ptr + i));
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}
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fprintf(logfile, "\n");
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}
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#endif
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count++;
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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if (env->psret == 0) {
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cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
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return;
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}
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#endif
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env->psret = 0;
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cwp = (env->cwp - 1) & (NWINDOWS - 1);
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set_cwp(cwp);
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env->regwptr[9] = env->pc;
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env->regwptr[10] = env->npc;
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env->psrps = env->psrs;
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env->psrs = 1;
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env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
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env->pc = env->tbr;
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env->npc = env->pc + 4;
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env->exception_index = 0;
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}
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target_ulong mmu_probe(target_ulong address, int mmulev)
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{
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target_phys_addr_t pde_ptr;
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uint32_t pde;
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 2: /* PTE, maybe should not happen? */
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case 3: /* Reserved */
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return 0;
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case 1: /* L1 PDE */
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if (mmulev == 3)
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return pde;
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 3: /* Reserved */
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return 0;
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case 2: /* L1 PTE */
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return pde;
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case 1: /* L2 PDE */
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if (mmulev == 2)
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return pde;
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 3: /* Reserved */
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return 0;
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case 2: /* L2 PTE */
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return pde;
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case 1: /* L3 PDE */
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if (mmulev == 1)
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return pde;
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 1: /* PDE, should not happen */
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case 3: /* Reserved */
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return 0;
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case 2: /* L3 PTE */
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return pde;
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}
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}
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}
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}
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return 0;
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}
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#ifdef DEBUG_MMU
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void dump_mmu(void)
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{
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target_ulong va, va1, va2;
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unsigned int n, m, o;
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target_phys_addr_t pde_ptr, pa;
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uint32_t pde;
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printf("MMU dump:\n");
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
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pde = ldl_phys(pde_ptr);
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printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
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pde_ptr = mmu_probe(va, 2);
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if (pde_ptr) {
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pa = cpu_get_phys_page_debug(env, va);
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
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for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
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pde_ptr = mmu_probe(va1, 1);
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if (pde_ptr) {
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pa = cpu_get_phys_page_debug(env, va1);
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printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
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for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
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pde_ptr = mmu_probe(va2, 0);
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if (pde_ptr) {
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pa = cpu_get_phys_page_debug(env, va2);
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printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
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}
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}
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}
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}
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}
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}
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printf("MMU dump ends\n");
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}
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#endif
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