185 lines
5.1 KiB
C
185 lines
5.1 KiB
C
/*
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* QEMU IDE Emulation: mmio support (for embedded).
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/dma.h"
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#include <hw/ide/internal.h>
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/***********************************************************/
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/* MMIO based ide port
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* This emulates IDE device connected directly to the CPU bus without
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* dedicated ide controller, which is often seen on embedded boards.
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*/
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#define TYPE_MMIO_IDE "mmio-ide"
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#define MMIO_IDE(obj) OBJECT_CHECK(MMIOState, (obj), TYPE_MMIO_IDE)
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typedef struct MMIOIDEState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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IDEBus bus;
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uint32_t shift;
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qemu_irq irq;
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MemoryRegion iomem1, iomem2;
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} MMIOState;
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static void mmio_ide_reset(DeviceState *dev)
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{
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MMIOState *s = MMIO_IDE(dev);
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ide_bus_reset(&s->bus);
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}
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static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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MMIOState *s = opaque;
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addr >>= s->shift;
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if (addr & 7)
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return ide_ioport_read(&s->bus, addr);
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else
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return ide_data_readw(&s->bus, 0);
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}
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static void mmio_ide_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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MMIOState *s = opaque;
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addr >>= s->shift;
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if (addr & 7)
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ide_ioport_write(&s->bus, addr, val);
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else
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ide_data_writew(&s->bus, 0, val);
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}
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static const MemoryRegionOps mmio_ide_ops = {
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.read = mmio_ide_read,
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.write = mmio_ide_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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MMIOState *s= opaque;
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return ide_status_read(&s->bus, 0);
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}
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static void mmio_ide_cmd_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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MMIOState *s = opaque;
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ide_cmd_write(&s->bus, 0, val);
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}
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static const MemoryRegionOps mmio_ide_cs_ops = {
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.read = mmio_ide_status_read,
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.write = mmio_ide_cmd_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const VMStateDescription vmstate_ide_mmio = {
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.name = "mmio-ide",
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.version_id = 3,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_IDE_BUS(bus, MMIOState),
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VMSTATE_IDE_DRIVES(bus.ifs, MMIOState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
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{
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SysBusDevice *d = SYS_BUS_DEVICE(dev);
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MMIOState *s = MMIO_IDE(dev);
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ide_init2(&s->bus, s->irq);
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memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s,
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"ide-mmio.1", 16 << s->shift);
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memory_region_init_io(&s->iomem2, OBJECT(s), &mmio_ide_cs_ops, s,
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"ide-mmio.2", 2 << s->shift);
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sysbus_init_mmio(d, &s->iomem1);
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sysbus_init_mmio(d, &s->iomem2);
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}
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static void mmio_ide_initfn(Object *obj)
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{
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SysBusDevice *d = SYS_BUS_DEVICE(obj);
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MMIOState *s = MMIO_IDE(obj);
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ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
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sysbus_init_irq(d, &s->irq);
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}
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static Property mmio_ide_properties[] = {
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DEFINE_PROP_UINT32("shift", MMIOState, shift, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void mmio_ide_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = mmio_ide_realizefn;
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dc->reset = mmio_ide_reset;
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dc->props = mmio_ide_properties;
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dc->vmsd = &vmstate_ide_mmio;
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}
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static const TypeInfo mmio_ide_type_info = {
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.name = TYPE_MMIO_IDE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MMIOState),
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.instance_init = mmio_ide_initfn,
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.class_init = mmio_ide_class_init,
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};
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static void mmio_ide_register_types(void)
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{
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type_register_static(&mmio_ide_type_info);
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}
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void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1)
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{
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MMIOState *s = MMIO_IDE(dev);
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if (hd0 != NULL) {
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ide_create_drive(&s->bus, 0, hd0);
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}
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if (hd1 != NULL) {
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ide_create_drive(&s->bus, 1, hd1);
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}
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}
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type_init(mmio_ide_register_types)
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