660 lines
20 KiB
C
660 lines
20 KiB
C
/*
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* Status and system control registers for ARM RealView/Versatile boards.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "qemu/timer.h"
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#include "qemu/bitops.h"
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#include "hw/sysbus.h"
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#include "hw/arm/primecell.h"
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#define LOCK_VALUE 0xa05f
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#define TYPE_ARM_SYSCTL "realview_sysctl"
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#define ARM_SYSCTL(obj) \
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OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL)
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typedef struct {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq pl110_mux_ctrl;
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uint32_t sys_id;
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uint32_t leds;
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uint16_t lockval;
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uint32_t cfgdata1;
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uint32_t cfgdata2;
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uint32_t flags;
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uint32_t nvflags;
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uint32_t resetlevel;
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uint32_t proc_id;
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uint32_t sys_mci;
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uint32_t sys_cfgdata;
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uint32_t sys_cfgctrl;
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uint32_t sys_cfgstat;
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uint32_t sys_clcd;
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uint32_t mb_clock[6];
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uint32_t *db_clock;
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uint32_t db_num_vsensors;
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uint32_t *db_voltage;
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uint32_t db_num_clocks;
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uint32_t *db_clock_reset;
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} arm_sysctl_state;
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static const VMStateDescription vmstate_arm_sysctl = {
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.name = "realview_sysctl",
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.version_id = 4,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(leds, arm_sysctl_state),
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VMSTATE_UINT16(lockval, arm_sysctl_state),
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VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
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VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
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VMSTATE_UINT32(flags, arm_sysctl_state),
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VMSTATE_UINT32(nvflags, arm_sysctl_state),
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VMSTATE_UINT32(resetlevel, arm_sysctl_state),
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VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
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VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
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VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
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4, vmstate_info_uint32, uint32_t),
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VMSTATE_END_OF_LIST()
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}
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};
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/* The PB926 actually uses a different format for
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* its SYS_ID register. Fortunately the bits which are
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* board type on later boards are distinct.
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*/
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#define BOARD_ID_PB926 0x100
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#define BOARD_ID_EB 0x140
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#define BOARD_ID_PBA8 0x178
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#define BOARD_ID_PBX 0x182
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#define BOARD_ID_VEXPRESS 0x190
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static int board_id(arm_sysctl_state *s)
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{
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/* Extract the board ID field from the SYS_ID register value */
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return (s->sys_id >> 16) & 0xfff;
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}
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static void arm_sysctl_reset(DeviceState *d)
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{
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arm_sysctl_state *s = ARM_SYSCTL(d);
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int i;
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s->leds = 0;
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s->lockval = 0;
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s->cfgdata1 = 0;
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s->cfgdata2 = 0;
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s->flags = 0;
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s->resetlevel = 0;
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/* Motherboard oscillators (in Hz) */
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s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
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s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
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s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
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s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
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s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
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s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
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/* Daughterboard oscillators: reset from property values */
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for (i = 0; i < s->db_num_clocks; i++) {
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s->db_clock[i] = s->db_clock_reset[i];
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}
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if (board_id(s) == BOARD_ID_VEXPRESS) {
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/* On VExpress this register will RAZ/WI */
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s->sys_clcd = 0;
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} else {
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/* All others: CLCDID 0x1f, indicating VGA */
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s->sys_clcd = 0x1f00;
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}
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}
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static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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arm_sysctl_state *s = (arm_sysctl_state *)opaque;
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switch (offset) {
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case 0x00: /* ID */
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return s->sys_id;
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case 0x04: /* SW */
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/* General purpose hardware switches.
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We don't have a useful way of exposing these to the user. */
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return 0;
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case 0x08: /* LED */
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return s->leds;
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case 0x20: /* LOCK */
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return s->lockval;
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case 0x0c: /* OSC0 */
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case 0x10: /* OSC1 */
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case 0x14: /* OSC2 */
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case 0x18: /* OSC3 */
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case 0x1c: /* OSC4 */
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case 0x24: /* 100HZ */
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/* ??? Implement these. */
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return 0;
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case 0x28: /* CFGDATA1 */
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return s->cfgdata1;
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case 0x2c: /* CFGDATA2 */
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return s->cfgdata2;
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case 0x30: /* FLAGS */
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return s->flags;
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case 0x38: /* NVFLAGS */
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return s->nvflags;
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case 0x40: /* RESETCTL */
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if (board_id(s) == BOARD_ID_VEXPRESS) {
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/* reserved: RAZ/WI */
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return 0;
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}
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return s->resetlevel;
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case 0x44: /* PCICTL */
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return 1;
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case 0x48: /* MCI */
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return s->sys_mci;
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case 0x4c: /* FLASH */
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return 0;
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case 0x50: /* CLCD */
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return s->sys_clcd;
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case 0x54: /* CLCDSER */
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return 0;
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case 0x58: /* BOOTCS */
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return 0;
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case 0x5c: /* 24MHz */
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return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000,
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NANOSECONDS_PER_SECOND);
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case 0x60: /* MISC */
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return 0;
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case 0x84: /* PROCID0 */
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return s->proc_id;
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case 0x88: /* PROCID1 */
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return 0xff000000;
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case 0x64: /* DMAPSR0 */
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case 0x68: /* DMAPSR1 */
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case 0x6c: /* DMAPSR2 */
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case 0x70: /* IOSEL */
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case 0x74: /* PLDCTL */
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case 0x80: /* BUSID */
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case 0x8c: /* OSCRESET0 */
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case 0x90: /* OSCRESET1 */
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case 0x94: /* OSCRESET2 */
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case 0x98: /* OSCRESET3 */
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case 0x9c: /* OSCRESET4 */
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case 0xc0: /* SYS_TEST_OSC0 */
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case 0xc4: /* SYS_TEST_OSC1 */
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case 0xc8: /* SYS_TEST_OSC2 */
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case 0xcc: /* SYS_TEST_OSC3 */
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case 0xd0: /* SYS_TEST_OSC4 */
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return 0;
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case 0xa0: /* SYS_CFGDATA */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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return s->sys_cfgdata;
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case 0xa4: /* SYS_CFGCTRL */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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return s->sys_cfgctrl;
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case 0xa8: /* SYS_CFGSTAT */
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if (board_id(s) != BOARD_ID_VEXPRESS) {
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goto bad_reg;
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}
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return s->sys_cfgstat;
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default:
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bad_reg:
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qemu_log_mask(LOG_GUEST_ERROR,
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"arm_sysctl_read: Bad register offset 0x%x\n",
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(int)offset);
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return 0;
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}
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}
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/* SYS_CFGCTRL functions */
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#define SYS_CFG_OSC 1
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#define SYS_CFG_VOLT 2
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#define SYS_CFG_AMP 3
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#define SYS_CFG_TEMP 4
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#define SYS_CFG_RESET 5
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#define SYS_CFG_SCC 6
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#define SYS_CFG_MUXFPGA 7
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#define SYS_CFG_SHUTDOWN 8
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#define SYS_CFG_REBOOT 9
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#define SYS_CFG_DVIMODE 11
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#define SYS_CFG_POWER 12
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#define SYS_CFG_ENERGY 13
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/* SYS_CFGCTRL site field values */
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#define SYS_CFG_SITE_MB 0
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#define SYS_CFG_SITE_DB1 1
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#define SYS_CFG_SITE_DB2 2
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/**
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* vexpress_cfgctrl_read:
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* @s: arm_sysctl_state pointer
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* @dcc, @function, @site, @position, @device: split out values from
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* SYS_CFGCTRL register
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* @val: pointer to where to put the read data on success
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*
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* Handle a VExpress SYS_CFGCTRL register read. On success, return true and
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* write the read value to *val. On failure, return false (and val may
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* or may not be written to).
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*/
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static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
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unsigned int function, unsigned int site,
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unsigned int position, unsigned int device,
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uint32_t *val)
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{
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/* We don't support anything other than DCC 0, board stack position 0
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* or sites other than motherboard/daughterboard:
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*/
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if (dcc != 0 || position != 0 ||
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(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
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goto cfgctrl_unimp;
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}
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switch (function) {
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case SYS_CFG_VOLT:
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if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) {
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*val = s->db_voltage[device];
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return true;
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}
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if (site == SYS_CFG_SITE_MB && device == 0) {
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/* There is only one motherboard voltage sensor:
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* VIO : 3.3V : bus voltage between mother and daughterboard
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*/
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*val = 3300000;
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return true;
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}
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break;
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case SYS_CFG_OSC:
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if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {
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/* motherboard clock */
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*val = s->mb_clock[device];
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return true;
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}
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if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
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/* daughterboard clock */
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*val = s->db_clock[device];
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return true;
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}
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break;
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default:
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break;
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}
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cfgctrl_unimp:
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qemu_log_mask(LOG_UNIMP,
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"arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
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"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
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function, dcc, site, position, device);
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return false;
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}
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/**
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* vexpress_cfgctrl_write:
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* @s: arm_sysctl_state pointer
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* @dcc, @function, @site, @position, @device: split out values from
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* SYS_CFGCTRL register
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* @val: data to write
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*
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* Handle a VExpress SYS_CFGCTRL register write. On success, return true.
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* On failure, return false.
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*/
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static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
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unsigned int function, unsigned int site,
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unsigned int position, unsigned int device,
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uint32_t val)
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{
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/* We don't support anything other than DCC 0, board stack position 0
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* or sites other than motherboard/daughterboard:
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*/
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if (dcc != 0 || position != 0 ||
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(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
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goto cfgctrl_unimp;
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}
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switch (function) {
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case SYS_CFG_OSC:
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if (site == SYS_CFG_SITE_MB && device < ARRAY_SIZE(s->mb_clock)) {
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/* motherboard clock */
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s->mb_clock[device] = val;
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return true;
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}
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if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
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/* daughterboard clock */
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s->db_clock[device] = val;
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return true;
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}
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break;
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case SYS_CFG_MUXFPGA:
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if (site == SYS_CFG_SITE_MB && device == 0) {
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/* Select whether video output comes from motherboard
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* or daughterboard: log and ignore as QEMU doesn't
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* support this.
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*/
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qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
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"not supported, ignoring\n");
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return true;
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}
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break;
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case SYS_CFG_SHUTDOWN:
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if (site == SYS_CFG_SITE_MB && device == 0) {
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qemu_system_shutdown_request();
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return true;
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}
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break;
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case SYS_CFG_REBOOT:
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if (site == SYS_CFG_SITE_MB && device == 0) {
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qemu_system_reset_request();
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return true;
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}
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break;
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case SYS_CFG_DVIMODE:
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if (site == SYS_CFG_SITE_MB && device == 0) {
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/* Selecting DVI mode is meaningless for QEMU: we will
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* always display the output correctly according to the
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* pixel height/width programmed into the CLCD controller.
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*/
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return true;
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}
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default:
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break;
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}
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cfgctrl_unimp:
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qemu_log_mask(LOG_UNIMP,
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"arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
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"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
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function, dcc, site, position, device);
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return false;
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}
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static void arm_sysctl_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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arm_sysctl_state *s = (arm_sysctl_state *)opaque;
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switch (offset) {
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case 0x08: /* LED */
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s->leds = val;
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break;
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case 0x0c: /* OSC0 */
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case 0x10: /* OSC1 */
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case 0x14: /* OSC2 */
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case 0x18: /* OSC3 */
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case 0x1c: /* OSC4 */
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/* ??? */
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break;
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case 0x20: /* LOCK */
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if (val == LOCK_VALUE)
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s->lockval = val;
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else
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s->lockval = val & 0x7fff;
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break;
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case 0x28: /* CFGDATA1 */
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/* ??? Need to implement this. */
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s->cfgdata1 = val;
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break;
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case 0x2c: /* CFGDATA2 */
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/* ??? Need to implement this. */
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s->cfgdata2 = val;
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break;
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case 0x30: /* FLAGSSET */
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s->flags |= val;
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break;
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case 0x34: /* FLAGSCLR */
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s->flags &= ~val;
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break;
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case 0x38: /* NVFLAGSSET */
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s->nvflags |= val;
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break;
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case 0x3c: /* NVFLAGSCLR */
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s->nvflags &= ~val;
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break;
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case 0x40: /* RESETCTL */
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switch (board_id(s)) {
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case BOARD_ID_PB926:
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if (s->lockval == LOCK_VALUE) {
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s->resetlevel = val;
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if (val & 0x100) {
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qemu_system_reset_request();
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}
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}
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break;
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case BOARD_ID_PBX:
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case BOARD_ID_PBA8:
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if (s->lockval == LOCK_VALUE) {
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s->resetlevel = val;
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if (val & 0x04) {
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qemu_system_reset_request();
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}
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}
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break;
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case BOARD_ID_VEXPRESS:
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case BOARD_ID_EB:
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default:
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/* reserved: RAZ/WI */
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break;
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}
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break;
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case 0x44: /* PCICTL */
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/* nothing to do. */
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break;
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case 0x4c: /* FLASH */
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break;
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case 0x50: /* CLCD */
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switch (board_id(s)) {
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case BOARD_ID_PB926:
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/* On 926 bits 13:8 are R/O, bits 1:0 control
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* the mux that defines how to interpret the PL110
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* graphics format, and other bits are r/w but we
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* don't implement them to do anything.
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*/
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s->sys_clcd &= 0x3f00;
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s->sys_clcd |= val & ~0x3f00;
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qemu_set_irq(s->pl110_mux_ctrl, val & 3);
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break;
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case BOARD_ID_EB:
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/* The EB is the same except that there is no mux since
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* the EB has a PL111.
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*/
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s->sys_clcd &= 0x3f00;
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s->sys_clcd |= val & ~0x3f00;
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break;
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case BOARD_ID_PBA8:
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case BOARD_ID_PBX:
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/* On PBA8 and PBX bit 7 is r/w and all other bits
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* are either r/o or RAZ/WI.
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*/
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s->sys_clcd &= (1 << 7);
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s->sys_clcd |= val & ~(1 << 7);
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break;
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case BOARD_ID_VEXPRESS:
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default:
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/* On VExpress this register is unimplemented and will RAZ/WI */
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break;
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}
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break;
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case 0x54: /* CLCDSER */
|
|
case 0x64: /* DMAPSR0 */
|
|
case 0x68: /* DMAPSR1 */
|
|
case 0x6c: /* DMAPSR2 */
|
|
case 0x70: /* IOSEL */
|
|
case 0x74: /* PLDCTL */
|
|
case 0x80: /* BUSID */
|
|
case 0x84: /* PROCID0 */
|
|
case 0x88: /* PROCID1 */
|
|
case 0x8c: /* OSCRESET0 */
|
|
case 0x90: /* OSCRESET1 */
|
|
case 0x94: /* OSCRESET2 */
|
|
case 0x98: /* OSCRESET3 */
|
|
case 0x9c: /* OSCRESET4 */
|
|
break;
|
|
case 0xa0: /* SYS_CFGDATA */
|
|
if (board_id(s) != BOARD_ID_VEXPRESS) {
|
|
goto bad_reg;
|
|
}
|
|
s->sys_cfgdata = val;
|
|
return;
|
|
case 0xa4: /* SYS_CFGCTRL */
|
|
if (board_id(s) != BOARD_ID_VEXPRESS) {
|
|
goto bad_reg;
|
|
}
|
|
/* Undefined bits [19:18] are RAZ/WI, and writing to
|
|
* the start bit just triggers the action; it always reads
|
|
* as zero.
|
|
*/
|
|
s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
|
|
if (val & (1 << 31)) {
|
|
/* Start bit set -- actually do something */
|
|
unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
|
|
unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
|
|
unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
|
|
unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
|
|
unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
|
|
s->sys_cfgstat = 1; /* complete */
|
|
if (s->sys_cfgctrl & (1 << 30)) {
|
|
if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
|
|
device, s->sys_cfgdata)) {
|
|
s->sys_cfgstat |= 2; /* error */
|
|
}
|
|
} else {
|
|
uint32_t val;
|
|
if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
|
|
device, &val)) {
|
|
s->sys_cfgstat |= 2; /* error */
|
|
} else {
|
|
s->sys_cfgdata = val;
|
|
}
|
|
}
|
|
}
|
|
s->sys_cfgctrl &= ~(1 << 31);
|
|
return;
|
|
case 0xa8: /* SYS_CFGSTAT */
|
|
if (board_id(s) != BOARD_ID_VEXPRESS) {
|
|
goto bad_reg;
|
|
}
|
|
s->sys_cfgstat = val & 3;
|
|
return;
|
|
default:
|
|
bad_reg:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"arm_sysctl_write: Bad register offset 0x%x\n",
|
|
(int)offset);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps arm_sysctl_ops = {
|
|
.read = arm_sysctl_read,
|
|
.write = arm_sysctl_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void arm_sysctl_gpio_set(void *opaque, int line, int level)
|
|
{
|
|
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
|
|
switch (line) {
|
|
case ARM_SYSCTL_GPIO_MMC_WPROT:
|
|
{
|
|
/* For PB926 and EB write-protect is bit 2 of SYS_MCI;
|
|
* for all later boards it is bit 1.
|
|
*/
|
|
int bit = 2;
|
|
if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
|
|
bit = 4;
|
|
}
|
|
s->sys_mci &= ~bit;
|
|
if (level) {
|
|
s->sys_mci |= bit;
|
|
}
|
|
break;
|
|
}
|
|
case ARM_SYSCTL_GPIO_MMC_CARDIN:
|
|
s->sys_mci &= ~1;
|
|
if (level) {
|
|
s->sys_mci |= 1;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void arm_sysctl_init(Object *obj)
|
|
{
|
|
DeviceState *dev = DEVICE(obj);
|
|
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
|
|
arm_sysctl_state *s = ARM_SYSCTL(obj);
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s,
|
|
"arm-sysctl", 0x1000);
|
|
sysbus_init_mmio(sd, &s->iomem);
|
|
qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);
|
|
qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);
|
|
}
|
|
|
|
static void arm_sysctl_realize(DeviceState *d, Error **errp)
|
|
{
|
|
arm_sysctl_state *s = ARM_SYSCTL(d);
|
|
|
|
s->db_clock = g_new0(uint32_t, s->db_num_clocks);
|
|
}
|
|
|
|
static void arm_sysctl_finalize(Object *obj)
|
|
{
|
|
arm_sysctl_state *s = ARM_SYSCTL(obj);
|
|
|
|
g_free(s->db_voltage);
|
|
g_free(s->db_clock);
|
|
g_free(s->db_clock_reset);
|
|
}
|
|
|
|
static Property arm_sysctl_properties[] = {
|
|
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
|
|
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
|
|
/* Daughterboard power supply voltages (as reported via SYS_CFG) */
|
|
DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors,
|
|
db_voltage, qdev_prop_uint32, uint32_t),
|
|
/* Daughterboard clock reset values (as reported via SYS_CFG) */
|
|
DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks,
|
|
db_clock_reset, qdev_prop_uint32, uint32_t),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void arm_sysctl_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = arm_sysctl_realize;
|
|
dc->reset = arm_sysctl_reset;
|
|
dc->vmsd = &vmstate_arm_sysctl;
|
|
dc->props = arm_sysctl_properties;
|
|
}
|
|
|
|
static const TypeInfo arm_sysctl_info = {
|
|
.name = TYPE_ARM_SYSCTL,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(arm_sysctl_state),
|
|
.instance_init = arm_sysctl_init,
|
|
.instance_finalize = arm_sysctl_finalize,
|
|
.class_init = arm_sysctl_class_init,
|
|
};
|
|
|
|
static void arm_sysctl_register_types(void)
|
|
{
|
|
type_register_static(&arm_sysctl_info);
|
|
}
|
|
|
|
type_init(arm_sysctl_register_types)
|