qemu-e2k/target
Peter Maydell 2c35a39eda target/arm: Convert Neon one-register-and-immediate insns to decodetree
Convert the insns in the one-register-and-immediate group to decodetree.

In the new decode, our asimd_imm_const() function returns a 64-bit value
rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
as a special case in the decoder (it is the only encoding where the two
halves of the 64-bit value are different).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
2020-06-05 17:23:10 +01:00
..
alpha accel/tcg: Relax va restrictions on 64-bit guests 2020-05-15 15:25:16 +01:00
arm target/arm: Convert Neon one-register-and-immediate insns to decodetree 2020-06-05 17:23:10 +01:00
cris
hppa softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
i386 i386: Fix x86_cpu_load_model() error API violation 2020-05-27 07:45:45 +02:00
lm32
m68k target/m68k: implement opcode fetoxm1 2020-06-02 13:59:02 +02:00
microblaze
mips target/mips: Support variable page size 2020-06-01 13:28:21 +02:00
moxie
nios2
openrisc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
ppc target/ppc: Use tcg_gen_gvec_rotlv 2020-06-02 08:42:37 -07:00
riscv target/riscv: Add the lowRISC Ibex CPU 2020-06-03 09:11:51 -07:00
rx
s390x target/s390x: Use tcg_gen_gvec_rotl{i,s,v} 2020-06-02 08:42:37 -07:00
sh4
sparc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
tilegx
tricore target/tricore: Implement gdbstub 2020-06-01 16:55:13 +02:00
unicore32 softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
xtensa softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00