2c4d3a501e
This change will help us move the mapping of XSCOM regions under the PHB3 realize routine, which will be necessary for user created PHB3 devices. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211213132830.108372-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
/*
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* QEMU PowerPC PowerNV (POWER8) PHB3 model
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*
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* Copyright (c) 2014-2020, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PCI_HOST_PNV_PHB3_H
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#define PCI_HOST_PNV_PHB3_H
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/ppc/xics.h"
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#include "qom/object.h"
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typedef struct PnvPHB3 PnvPHB3;
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typedef struct PnvChip PnvChip;
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/*
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* PHB3 XICS Source for MSIs
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*/
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#define TYPE_PHB3_MSI "phb3-msi"
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typedef struct Phb3MsiState Phb3MsiState;
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DECLARE_INSTANCE_CHECKER(Phb3MsiState, PHB3_MSI,
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TYPE_PHB3_MSI)
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#define PHB3_MAX_MSI 2048
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struct Phb3MsiState {
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ICSState ics;
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qemu_irq *qirqs;
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PnvPHB3 *phb;
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uint64_t rba[PHB3_MAX_MSI / 64];
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uint32_t rba_sum;
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};
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void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
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uint32_t count);
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void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
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int32_t dev_pe);
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void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
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void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon);
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/*
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* We have one such address space wrapper per possible device under
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* the PHB since they need to be assigned statically at qemu device
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* creation time. The relationship to a PE is done later dynamically.
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* This means we can potentially create a lot of these guys. Q35
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* stores them as some kind of radix tree but we never really need to
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* do fast lookups so instead we simply keep a QLIST of them for now,
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* we can add the radix if needed later on.
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*
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* We do cache the PE number to speed things up a bit though.
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*/
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typedef struct PnvPhb3DMASpace {
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PCIBus *bus;
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uint8_t devfn;
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int pe_num; /* Cached PE number */
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#define PHB_INVALID_PE (-1)
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PnvPHB3 *phb;
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AddressSpace dma_as;
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IOMMUMemoryRegion dma_mr;
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MemoryRegion msi32_mr;
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MemoryRegion msi64_mr;
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QLIST_ENTRY(PnvPhb3DMASpace) list;
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} PnvPhb3DMASpace;
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/*
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* PHB3 Power Bus Common Queue
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*/
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#define TYPE_PNV_PBCQ "pnv-pbcq"
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OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ)
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struct PnvPBCQState {
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DeviceState parent;
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uint32_t nest_xbase;
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uint32_t spci_xbase;
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uint32_t pci_xbase;
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#define PBCQ_NEST_REGS_COUNT 0x46
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#define PBCQ_PCI_REGS_COUNT 0x15
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#define PBCQ_SPCI_REGS_COUNT 0x5
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uint64_t nest_regs[PBCQ_NEST_REGS_COUNT];
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uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT];
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uint64_t pci_regs[PBCQ_PCI_REGS_COUNT];
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MemoryRegion mmbar0;
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MemoryRegion mmbar1;
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MemoryRegion phbbar;
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uint64_t mmio0_base;
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uint64_t mmio0_size;
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uint64_t mmio1_base;
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uint64_t mmio1_size;
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PnvPHB3 *phb;
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MemoryRegion xscom_nest_regs;
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MemoryRegion xscom_pci_regs;
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MemoryRegion xscom_spci_regs;
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};
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/*
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* PHB3 PCIe Root port
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*/
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#define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root-bus"
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#define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port"
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typedef struct PnvPHB3RootPort {
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PCIESlot parent_obj;
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} PnvPHB3RootPort;
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/*
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* PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
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*/
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#define TYPE_PNV_PHB3 "pnv-phb3"
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OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
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#define PNV_PHB3_NUM_M64 16
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#define PNV_PHB3_NUM_REGS (0x1000 >> 3)
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#define PNV_PHB3_NUM_LSI 8
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#define PNV_PHB3_NUM_PE 256
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#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
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struct PnvPHB3 {
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PCIExpressHost parent_obj;
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uint32_t chip_id;
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uint32_t phb_id;
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char bus_path[8];
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uint64_t regs[PNV_PHB3_NUM_REGS];
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MemoryRegion mr_regs;
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MemoryRegion mr_m32;
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MemoryRegion mr_m64[PNV_PHB3_NUM_M64];
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MemoryRegion pci_mmio;
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MemoryRegion pci_io;
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uint64_t ioda_LIST[8];
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uint64_t ioda_LXIVT[8];
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uint64_t ioda_TVT[512];
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uint64_t ioda_M64BT[16];
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uint64_t ioda_MDT[256];
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uint64_t ioda_PEEV[4];
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uint32_t total_irq;
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ICSState lsis;
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qemu_irq *qirqs;
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Phb3MsiState msis;
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PnvPBCQState pbcq;
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PnvPHB3RootPort root;
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QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
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PnvChip *chip;
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};
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uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
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void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
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void pnv_phb3_update_regions(PnvPHB3 *phb);
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void pnv_phb3_remap_irqs(PnvPHB3 *phb);
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#endif /* PCI_HOST_PNV_PHB3_H */
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