f32393ac0a
Remove these confusing and unused definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210127232151.3523581-6-f4bug@amsat.org>
382 lines
13 KiB
C
382 lines
13 KiB
C
/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SH4_CPU_H
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#define SH4_CPU_H
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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/* CPU Subtypes */
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#define SH_CPU_SH7750 (1 << 0)
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#define SH_CPU_SH7750S (1 << 1)
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#define SH_CPU_SH7750R (1 << 2)
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#define SH_CPU_SH7751 (1 << 3)
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#define SH_CPU_SH7751R (1 << 4)
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#define SH_CPU_SH7785 (1 << 5)
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#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
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#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
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#define SR_MD 30
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#define SR_RB 29
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#define SR_BL 28
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#define SR_FD 15
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#define SR_M 9
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#define SR_Q 8
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#define SR_I3 7
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#define SR_I2 6
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#define SR_I1 5
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#define SR_I0 4
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#define SR_S 1
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#define SR_T 0
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#define FPSCR_MASK (0x003fffff)
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#define FPSCR_FR (1 << 21)
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#define FPSCR_SZ (1 << 20)
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#define FPSCR_PR (1 << 19)
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#define FPSCR_DN (1 << 18)
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#define FPSCR_CAUSE_MASK (0x3f << 12)
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#define FPSCR_CAUSE_SHIFT (12)
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#define FPSCR_CAUSE_E (1 << 17)
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#define FPSCR_CAUSE_V (1 << 16)
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#define FPSCR_CAUSE_Z (1 << 15)
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#define FPSCR_CAUSE_O (1 << 14)
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#define FPSCR_CAUSE_U (1 << 13)
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#define FPSCR_CAUSE_I (1 << 12)
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#define FPSCR_ENABLE_MASK (0x1f << 7)
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#define FPSCR_ENABLE_SHIFT (7)
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#define FPSCR_ENABLE_V (1 << 11)
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#define FPSCR_ENABLE_Z (1 << 10)
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#define FPSCR_ENABLE_O (1 << 9)
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#define FPSCR_ENABLE_U (1 << 8)
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#define FPSCR_ENABLE_I (1 << 7)
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#define FPSCR_FLAG_MASK (0x1f << 2)
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#define FPSCR_FLAG_SHIFT (2)
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#define FPSCR_FLAG_V (1 << 6)
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#define FPSCR_FLAG_Z (1 << 5)
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#define FPSCR_FLAG_O (1 << 4)
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#define FPSCR_FLAG_U (1 << 3)
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#define FPSCR_FLAG_I (1 << 2)
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#define FPSCR_RM_MASK (0x03 << 0)
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#define FPSCR_RM_NEAREST (0 << 0)
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#define FPSCR_RM_ZERO (1 << 0)
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#define DELAY_SLOT_MASK 0x7
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#define DELAY_SLOT (1 << 0)
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#define DELAY_SLOT_CONDITIONAL (1 << 1)
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#define DELAY_SLOT_RTE (1 << 2)
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#define TB_FLAG_PENDING_MOVCA (1 << 3)
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#define GUSA_SHIFT 4
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#ifdef CONFIG_USER_ONLY
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#define GUSA_EXCLUSIVE (1 << 12)
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#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
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#else
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/* Provide dummy versions of the above to allow tests against tbflags
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to be elided while avoiding ifdefs. */
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#define GUSA_EXCLUSIVE 0
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#define GUSA_MASK 0
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#endif
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#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK)
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typedef struct tlb_t {
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uint32_t vpn; /* virtual page number */
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uint32_t ppn; /* physical page number */
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uint32_t size; /* mapped page size in bytes */
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uint8_t asid; /* address space identifier */
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uint8_t v:1; /* validity */
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uint8_t sz:2; /* page size */
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uint8_t sh:1; /* share status */
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uint8_t c:1; /* cacheability */
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uint8_t pr:2; /* protection key */
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uint8_t d:1; /* dirty */
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uint8_t wt:1; /* write through */
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uint8_t sa:3; /* space attribute (PCMCIA) */
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uint8_t tc:1; /* timing control */
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} tlb_t;
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#define UTLB_SIZE 64
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#define ITLB_SIZE 4
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#define TARGET_INSN_START_EXTRA_WORDS 1
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enum sh_features {
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SH_FEATURE_SH4A = 1,
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SH_FEATURE_BCR3_AND_BCR4 = 2,
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};
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typedef struct memory_content {
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uint32_t address;
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uint32_t value;
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struct memory_content *next;
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} memory_content;
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typedef struct CPUSH4State {
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uint32_t flags; /* general execution flags */
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uint32_t gregs[24]; /* general registers */
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float32 fregs[32]; /* floating point registers */
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uint32_t sr; /* status register (with T split out) */
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uint32_t sr_m; /* M bit of status register */
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uint32_t sr_q; /* Q bit of status register */
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uint32_t sr_t; /* T bit of status register */
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uint32_t ssr; /* saved status register */
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uint32_t spc; /* saved program counter */
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uint32_t gbr; /* global base register */
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uint32_t vbr; /* vector base register */
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uint32_t sgr; /* saved global register 15 */
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uint32_t dbr; /* debug base register */
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uint32_t pc; /* program counter */
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uint32_t delayed_pc; /* target of delayed branch */
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uint32_t delayed_cond; /* condition of delayed branch */
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uint32_t mach; /* multiply and accumulate high */
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uint32_t macl; /* multiply and accumulate low */
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uint32_t pr; /* procedure register */
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uint32_t fpscr; /* floating point status/control register */
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uint32_t fpul; /* floating point communication register */
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/* float point status register */
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float_status fp_status;
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/* Those belong to the specific unit (SH7750) but are handled here */
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uint32_t mmucr; /* MMU control register */
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uint32_t pteh; /* page table entry high register */
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uint32_t ptel; /* page table entry low register */
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uint32_t ptea; /* page table entry assistance register */
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uint32_t ttb; /* translation table base register */
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uint32_t tea; /* TLB exception address register */
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uint32_t tra; /* TRAPA exception register */
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uint32_t expevt; /* exception event register */
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uint32_t intevt; /* interrupt event register */
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tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
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tlb_t utlb[UTLB_SIZE]; /* unified translation table */
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/* LDST = LOCK_ADDR != -1. */
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uint32_t lock_addr;
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uint32_t lock_value;
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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/* Fields from here on are preserved over CPU reset. */
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int id; /* CPU model */
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/* The features that we should emulate. See sh_features above. */
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uint32_t features;
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void *intc_handle;
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int in_sleep; /* SR_BL ignored during sleep */
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memory_content *movcal_backup;
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memory_content **movcal_backup_tail;
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} CPUSH4State;
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/**
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* SuperHCPU:
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* @env: #CPUSH4State
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*
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* A SuperH CPU.
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*/
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struct SuperHCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUSH4State env;
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};
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void superh_cpu_do_interrupt(CPUState *cpu);
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bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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void sh4_translate_init(void);
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int cpu_sh4_signal_handler(int host_signum, void *pinfo,
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void *puc);
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bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void sh4_cpu_list(void);
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#if !defined(CONFIG_USER_ONLY)
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void cpu_sh4_invalidate_tlb(CPUSH4State *s);
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uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
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hwaddr addr);
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void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
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uint32_t mem_value);
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uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
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hwaddr addr);
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void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
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uint32_t mem_value);
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uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
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hwaddr addr);
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void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
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uint32_t mem_value);
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uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
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hwaddr addr);
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void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
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uint32_t mem_value);
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#endif
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int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
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void cpu_load_tlb(CPUSH4State * env);
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#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
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#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
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#define cpu_signal_handler cpu_sh4_signal_handler
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#define cpu_list sh4_cpu_list
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/* MMU modes definitions */
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
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{
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/* The instruction in a RTE delay slot is fetched in privileged
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mode, but executed in user mode. */
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if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
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return 0;
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} else {
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return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
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}
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}
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typedef CPUSH4State CPUArchState;
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typedef SuperHCPU ArchCPU;
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#include "exec/cpu-all.h"
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/* MMU control register */
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#define MMUCR 0x1F000010
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#define MMUCR_AT (1<<0)
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#define MMUCR_TI (1<<2)
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#define MMUCR_SV (1<<8)
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#define MMUCR_URC_BITS (6)
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#define MMUCR_URC_OFFSET (10)
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#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
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#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
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static inline int cpu_mmucr_urc (uint32_t mmucr)
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{
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return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
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}
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/* PTEH : Page Translation Entry High register */
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#define PTEH_ASID_BITS (8)
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#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
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#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
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#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
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#define PTEH_VPN_BITS (22)
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#define PTEH_VPN_OFFSET (10)
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#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
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#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
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static inline int cpu_pteh_vpn (uint32_t pteh)
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{
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return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
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}
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/* PTEL : Page Translation Entry Low register */
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#define PTEL_V (1 << 8)
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#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
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#define PTEL_C (1 << 3)
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#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
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#define PTEL_D (1 << 2)
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#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
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#define PTEL_SH (1 << 1)
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#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
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#define PTEL_WT (1 << 0)
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#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
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#define PTEL_SZ_HIGH_OFFSET (7)
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#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
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#define PTEL_SZ_LOW_OFFSET (4)
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#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
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static inline int cpu_ptel_sz (uint32_t ptel)
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{
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int sz;
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sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
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sz <<= 1;
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sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
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return sz;
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}
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#define PTEL_PPN_BITS (19)
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#define PTEL_PPN_OFFSET (10)
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#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
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#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
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static inline int cpu_ptel_ppn (uint32_t ptel)
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{
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return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
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}
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#define PTEL_PR_BITS (2)
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#define PTEL_PR_OFFSET (5)
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#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
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#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
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static inline int cpu_ptel_pr (uint32_t ptel)
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{
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return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
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}
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/* PTEA : Page Translation Entry Assistance register */
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#define PTEA_SA_BITS (3)
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#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
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#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
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#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
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#define PTEA_TC (1 << 3)
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#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
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static inline target_ulong cpu_read_sr(CPUSH4State *env)
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{
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return env->sr | (env->sr_m << SR_M) |
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(env->sr_q << SR_Q) |
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(env->sr_t << SR_T);
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}
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static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
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{
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env->sr_m = (sr >> SR_M) & 1;
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env->sr_q = (sr >> SR_Q) & 1;
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env->sr_t = (sr >> SR_T) & 1;
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env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
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}
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static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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/* For a gUSA region, notice the end of the region. */
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*cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
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*flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
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| (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
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| (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
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| (env->sr & (1u << SR_FD)) /* Bit 15 */
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| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
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}
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#endif /* SH4_CPU_H */
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