2d258b428b
Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h, fcvt.h.d Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
794 lines
22 KiB
C
794 lines
22 KiB
C
/*
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* RISC-V emulation for qemu: main translation routines.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "tcg/tcg-op.h"
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#include "disas/disas.h"
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#include "exec/cpu_ldst.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "exec/translator.h"
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#include "exec/log.h"
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#include "instmap.h"
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/* global register indices */
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static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
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static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
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static TCGv load_res;
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static TCGv load_val;
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/* globals for PM CSRs */
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static TCGv pm_mask[4];
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static TCGv pm_base[4];
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#include "exec/gen-icount.h"
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/*
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* If an operation is being performed on less than TARGET_LONG_BITS,
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* it may require the inputs to be sign- or zero-extended; which will
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* depend on the exact operation being performed.
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*/
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typedef enum {
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EXT_NONE,
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EXT_SIGN,
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EXT_ZERO,
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} DisasExtend;
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typedef struct DisasContext {
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DisasContextBase base;
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/* pc_succ_insn points to the instruction following base.pc_next */
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target_ulong pc_succ_insn;
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target_ulong priv_ver;
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RISCVMXL xl;
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uint32_t misa_ext;
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uint32_t opcode;
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uint32_t mstatus_fs;
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uint32_t mstatus_hs_fs;
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uint32_t mem_idx;
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/* Remember the rounding mode encoded in the previous fp instruction,
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which we have already installed into env->fp_status. Or -1 for
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no previous fp instruction. Note that we exit the TB when writing
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to any system register, which includes CSR_FRM, so we do not have
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to reset this known value. */
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int frm;
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RISCVMXL ol;
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bool virt_enabled;
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bool ext_ifencei;
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bool ext_zfh;
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bool ext_zfhmin;
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bool hlsx;
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/* vector extension */
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bool vill;
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uint8_t lmul;
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uint8_t sew;
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uint16_t vlen;
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uint16_t mlen;
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bool vl_eq_vlmax;
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uint8_t ntemp;
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CPUState *cs;
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TCGv zero;
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/* Space for 3 operands plus 1 extra for address computation. */
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TCGv temp[4];
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/* PointerMasking extension */
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bool pm_enabled;
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TCGv pm_mask;
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TCGv pm_base;
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} DisasContext;
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static inline bool has_ext(DisasContext *ctx, uint32_t ext)
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{
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return ctx->misa_ext & ext;
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}
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#ifdef TARGET_RISCV32
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#define get_xl(ctx) MXL_RV32
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#elif defined(CONFIG_USER_ONLY)
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#define get_xl(ctx) MXL_RV64
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#else
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#define get_xl(ctx) ((ctx)->xl)
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#endif
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/* The word size for this machine mode. */
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static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
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{
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return 16 << get_xl(ctx);
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}
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/* The operation length, as opposed to the xlen. */
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#ifdef TARGET_RISCV32
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#define get_ol(ctx) MXL_RV32
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#else
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#define get_ol(ctx) ((ctx)->ol)
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#endif
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static inline int get_olen(DisasContext *ctx)
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{
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return 16 << get_ol(ctx);
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}
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/*
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* RISC-V requires NaN-boxing of narrower width floating point values.
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* This applies when a 32-bit value is assigned to a 64-bit FP register.
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* For consistency and simplicity, we nanbox results even when the RVD
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* extension is not present.
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*/
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static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
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{
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tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
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}
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static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
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{
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tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
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}
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/*
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* A narrow n-bit operation, where n < FLEN, checks that input operands
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* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
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* If so, the least-significant bits of the input are used, otherwise the
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* input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
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*
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* Here, the result is always nan-boxed, even the canonical nan.
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*/
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static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
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{
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TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
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TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
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tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
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tcg_temp_free_i64(t_max);
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tcg_temp_free_i64(t_nan);
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}
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static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
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{
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TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
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TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
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tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
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}
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static void generate_exception(DisasContext *ctx, int excp)
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{
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void generate_exception_mtval(DisasContext *ctx, int excp)
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{
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
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gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_exception_illegal(DisasContext *ctx)
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{
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generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
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}
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static void gen_exception_inst_addr_mis(DisasContext *ctx)
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{
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generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
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}
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static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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{
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if (translator_use_goto_tb(&ctx->base, dest)) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_exit_tb(ctx->base.tb, n);
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} else {
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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/*
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* Wrappers for getting reg values.
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*
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* The $zero register does not have cpu_gpr[0] allocated -- we supply the
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* constant zero as a source, and an uninitialized sink as destination.
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*
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* Further, we may provide an extension for word operations.
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*/
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static TCGv temp_new(DisasContext *ctx)
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{
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assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
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return ctx->temp[ctx->ntemp++] = tcg_temp_new();
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}
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static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
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{
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TCGv t;
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if (reg_num == 0) {
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return ctx->zero;
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}
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switch (get_ol(ctx)) {
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case MXL_RV32:
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switch (ext) {
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case EXT_NONE:
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break;
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case EXT_SIGN:
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t = temp_new(ctx);
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tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
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return t;
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case EXT_ZERO:
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t = temp_new(ctx);
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tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
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return t;
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default:
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g_assert_not_reached();
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}
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break;
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case MXL_RV64:
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break;
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default:
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g_assert_not_reached();
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}
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return cpu_gpr[reg_num];
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}
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static TCGv dest_gpr(DisasContext *ctx, int reg_num)
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{
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if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
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return temp_new(ctx);
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}
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return cpu_gpr[reg_num];
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}
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static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
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{
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if (reg_num != 0) {
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switch (get_ol(ctx)) {
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case MXL_RV32:
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tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
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break;
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case MXL_RV64:
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tcg_gen_mov_tl(cpu_gpr[reg_num], t);
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break;
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default:
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g_assert_not_reached();
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}
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}
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}
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static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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{
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target_ulong next_pc;
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/* check misaligned: */
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next_pc = ctx->base.pc_next + imm;
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if (!has_ext(ctx, RVC)) {
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if ((next_pc & 0x3) != 0) {
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gen_exception_inst_addr_mis(ctx);
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return;
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}
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}
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if (rd != 0) {
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tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
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}
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gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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/*
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* Generates address adjustment for PointerMasking
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*/
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static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
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{
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TCGv temp;
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if (!s->pm_enabled) {
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/* Load unmodified address */
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return src;
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} else {
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temp = temp_new(s);
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tcg_gen_andc_tl(temp, src, s->pm_mask);
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tcg_gen_or_tl(temp, temp, s->pm_base);
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return temp;
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}
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}
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#ifndef CONFIG_USER_ONLY
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/* The states of mstatus_fs are:
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* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
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* We will have already diagnosed disabled state,
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* and need to turn initial/clean into dirty.
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*/
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static void mark_fs_dirty(DisasContext *ctx)
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{
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TCGv tmp;
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if (ctx->mstatus_fs != MSTATUS_FS) {
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/* Remember the state change for the rest of the TB. */
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ctx->mstatus_fs = MSTATUS_FS;
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tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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tcg_temp_free(tmp);
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}
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if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
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/* Remember the stage change for the rest of the TB. */
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ctx->mstatus_hs_fs = MSTATUS_FS;
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tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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tcg_temp_free(tmp);
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}
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}
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#else
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static inline void mark_fs_dirty(DisasContext *ctx) { }
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#endif
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static void gen_set_rm(DisasContext *ctx, int rm)
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{
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if (ctx->frm == rm) {
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return;
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}
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ctx->frm = rm;
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gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
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}
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static int ex_plus_1(DisasContext *ctx, int nf)
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{
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return nf + 1;
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}
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#define EX_SH(amount) \
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static int ex_shift_##amount(DisasContext *ctx, int imm) \
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{ \
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return imm << amount; \
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}
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EX_SH(1)
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EX_SH(2)
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EX_SH(3)
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EX_SH(4)
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EX_SH(12)
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#define REQUIRE_EXT(ctx, ext) do { \
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if (!has_ext(ctx, ext)) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_32BIT(ctx) do { \
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if (get_xl(ctx) != MXL_RV32) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_64BIT(ctx) do { \
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if (get_xl(ctx) < MXL_RV64) { \
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return false; \
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} \
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} while (0)
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static int ex_rvc_register(DisasContext *ctx, int reg)
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{
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return 8 + reg;
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}
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static int ex_rvc_shifti(DisasContext *ctx, int imm)
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{
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/* For RV128 a shamt of 0 means a shift by 64. */
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return imm ? imm : 64;
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}
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/* Include the auto-generated decoder for 32 bit insn */
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#include "decode-insn32.c.inc"
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static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
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void (*func)(TCGv, TCGv, target_long))
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{
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv src1 = get_gpr(ctx, a->rs1, ext);
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func(dest, src1, a->imm);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
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}
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static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
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void (*func)(TCGv, TCGv, TCGv))
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{
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv src1 = get_gpr(ctx, a->rs1, ext);
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TCGv src2 = tcg_constant_tl(a->imm);
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func(dest, src1, src2);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
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}
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static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
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void (*func)(TCGv, TCGv, TCGv))
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{
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv src1 = get_gpr(ctx, a->rs1, ext);
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TCGv src2 = get_gpr(ctx, a->rs2, ext);
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func(dest, src1, src2);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
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}
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static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
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void (*f_tl)(TCGv, TCGv, TCGv),
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void (*f_32)(TCGv, TCGv, TCGv))
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{
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int olen = get_olen(ctx);
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if (olen != TARGET_LONG_BITS) {
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if (olen == 32) {
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f_tl = f_32;
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} else {
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g_assert_not_reached();
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}
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}
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return gen_arith(ctx, a, ext, f_tl);
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}
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static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
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void (*func)(TCGv, TCGv, target_long))
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{
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TCGv dest, src1;
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int max_len = get_olen(ctx);
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if (a->shamt >= max_len) {
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return false;
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}
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dest = dest_gpr(ctx, a->rd);
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src1 = get_gpr(ctx, a->rs1, ext);
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func(dest, src1, a->shamt);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
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}
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static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
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DisasExtend ext,
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void (*f_tl)(TCGv, TCGv, target_long),
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void (*f_32)(TCGv, TCGv, target_long))
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{
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int olen = get_olen(ctx);
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if (olen != TARGET_LONG_BITS) {
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if (olen == 32) {
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f_tl = f_32;
|
|
} else {
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
return gen_shift_imm_fn(ctx, a, ext, f_tl);
|
|
}
|
|
|
|
static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
|
|
void (*func)(TCGv, TCGv, TCGv))
|
|
{
|
|
TCGv dest, src1, src2;
|
|
int max_len = get_olen(ctx);
|
|
|
|
if (a->shamt >= max_len) {
|
|
return false;
|
|
}
|
|
|
|
dest = dest_gpr(ctx, a->rd);
|
|
src1 = get_gpr(ctx, a->rs1, ext);
|
|
src2 = tcg_constant_tl(a->shamt);
|
|
|
|
func(dest, src1, src2);
|
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
return true;
|
|
}
|
|
|
|
static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
|
|
void (*func)(TCGv, TCGv, TCGv))
|
|
{
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
|
TCGv src1 = get_gpr(ctx, a->rs1, ext);
|
|
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
|
|
TCGv ext2 = tcg_temp_new();
|
|
|
|
tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
|
|
func(dest, src1, ext2);
|
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
tcg_temp_free(ext2);
|
|
return true;
|
|
}
|
|
|
|
static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
|
|
void (*f_tl)(TCGv, TCGv, TCGv),
|
|
void (*f_32)(TCGv, TCGv, TCGv))
|
|
{
|
|
int olen = get_olen(ctx);
|
|
if (olen != TARGET_LONG_BITS) {
|
|
if (olen == 32) {
|
|
f_tl = f_32;
|
|
} else {
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
return gen_shift(ctx, a, ext, f_tl);
|
|
}
|
|
|
|
static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
|
|
void (*func)(TCGv, TCGv))
|
|
{
|
|
TCGv dest = dest_gpr(ctx, a->rd);
|
|
TCGv src1 = get_gpr(ctx, a->rs1, ext);
|
|
|
|
func(dest, src1);
|
|
|
|
gen_set_gpr(ctx, a->rd, dest);
|
|
return true;
|
|
}
|
|
|
|
static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
|
|
void (*f_tl)(TCGv, TCGv),
|
|
void (*f_32)(TCGv, TCGv))
|
|
{
|
|
int olen = get_olen(ctx);
|
|
|
|
if (olen != TARGET_LONG_BITS) {
|
|
if (olen == 32) {
|
|
f_tl = f_32;
|
|
} else {
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
return gen_unary(ctx, a, ext, f_tl);
|
|
}
|
|
|
|
static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
CPUState *cpu = ctx->cs;
|
|
CPURISCVState *env = cpu->env_ptr;
|
|
|
|
return cpu_ldl_code(env, pc);
|
|
}
|
|
|
|
/* Include insn module translation function */
|
|
#include "insn_trans/trans_rvi.c.inc"
|
|
#include "insn_trans/trans_rvm.c.inc"
|
|
#include "insn_trans/trans_rva.c.inc"
|
|
#include "insn_trans/trans_rvf.c.inc"
|
|
#include "insn_trans/trans_rvd.c.inc"
|
|
#include "insn_trans/trans_rvh.c.inc"
|
|
#include "insn_trans/trans_rvv.c.inc"
|
|
#include "insn_trans/trans_rvb.c.inc"
|
|
#include "insn_trans/trans_rvzfh.c.inc"
|
|
#include "insn_trans/trans_privileged.c.inc"
|
|
|
|
/* Include the auto-generated decoder for 16 bit insn */
|
|
#include "decode-insn16.c.inc"
|
|
|
|
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
|
|
{
|
|
/* check for compressed insn */
|
|
if (extract16(opcode, 0, 2) != 3) {
|
|
if (!has_ext(ctx, RVC)) {
|
|
gen_exception_illegal(ctx);
|
|
} else {
|
|
ctx->pc_succ_insn = ctx->base.pc_next + 2;
|
|
if (!decode_insn16(ctx, opcode)) {
|
|
gen_exception_illegal(ctx);
|
|
}
|
|
}
|
|
} else {
|
|
uint32_t opcode32 = opcode;
|
|
opcode32 = deposit32(opcode32, 16, 16,
|
|
translator_lduw(env, &ctx->base,
|
|
ctx->base.pc_next + 2));
|
|
ctx->pc_succ_insn = ctx->base.pc_next + 4;
|
|
if (!decode_insn32(ctx, opcode32)) {
|
|
gen_exception_illegal(ctx);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
CPURISCVState *env = cs->env_ptr;
|
|
RISCVCPU *cpu = RISCV_CPU(cs);
|
|
uint32_t tb_flags = ctx->base.tb->flags;
|
|
|
|
ctx->pc_succ_insn = ctx->base.pc_first;
|
|
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
|
|
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
|
|
ctx->priv_ver = env->priv_ver;
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
if (riscv_has_ext(env, RVH)) {
|
|
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
|
|
} else {
|
|
ctx->virt_enabled = false;
|
|
}
|
|
#else
|
|
ctx->virt_enabled = false;
|
|
#endif
|
|
ctx->misa_ext = env->misa_ext;
|
|
ctx->frm = -1; /* unknown rounding mode */
|
|
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
|
|
ctx->ext_zfh = cpu->cfg.ext_zfh;
|
|
ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
|
|
ctx->vlen = cpu->cfg.vlen;
|
|
ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
|
|
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
|
|
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
|
|
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
|
|
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
|
|
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
|
|
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
|
|
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
|
|
ctx->cs = cs;
|
|
ctx->ntemp = 0;
|
|
memset(ctx->temp, 0, sizeof(ctx->temp));
|
|
ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
|
|
int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
|
|
ctx->pm_mask = pm_mask[priv];
|
|
ctx->pm_base = pm_base[priv];
|
|
|
|
ctx->zero = tcg_constant_tl(0);
|
|
}
|
|
|
|
static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
|
|
{
|
|
}
|
|
|
|
static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
tcg_gen_insn_start(ctx->base.pc_next);
|
|
}
|
|
|
|
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
CPURISCVState *env = cpu->env_ptr;
|
|
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
|
|
|
|
ctx->ol = ctx->xl;
|
|
decode_opc(env, ctx, opcode16);
|
|
ctx->base.pc_next = ctx->pc_succ_insn;
|
|
|
|
for (int i = ctx->ntemp - 1; i >= 0; --i) {
|
|
tcg_temp_free(ctx->temp[i]);
|
|
ctx->temp[i] = NULL;
|
|
}
|
|
ctx->ntemp = 0;
|
|
|
|
if (ctx->base.is_jmp == DISAS_NEXT) {
|
|
target_ulong page_start;
|
|
|
|
page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
|
|
if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
|
|
ctx->base.is_jmp = DISAS_TOO_MANY;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
switch (ctx->base.is_jmp) {
|
|
case DISAS_TOO_MANY:
|
|
gen_goto_tb(ctx, 0, ctx->base.pc_next);
|
|
break;
|
|
case DISAS_NORETURN:
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
#ifndef CONFIG_USER_ONLY
|
|
RISCVCPU *rvcpu = RISCV_CPU(cpu);
|
|
CPURISCVState *env = &rvcpu->env;
|
|
#endif
|
|
|
|
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
|
|
#ifndef CONFIG_USER_ONLY
|
|
qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
|
|
#endif
|
|
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
|
|
}
|
|
|
|
static const TranslatorOps riscv_tr_ops = {
|
|
.init_disas_context = riscv_tr_init_disas_context,
|
|
.tb_start = riscv_tr_tb_start,
|
|
.insn_start = riscv_tr_insn_start,
|
|
.translate_insn = riscv_tr_translate_insn,
|
|
.tb_stop = riscv_tr_tb_stop,
|
|
.disas_log = riscv_tr_disas_log,
|
|
};
|
|
|
|
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
|
|
{
|
|
DisasContext ctx;
|
|
|
|
translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
|
|
}
|
|
|
|
void riscv_translate_init(void)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* cpu_gpr[0] is a placeholder for the zero register. Do not use it.
|
|
* Use the gen_set_gpr and get_gpr helper functions when accessing regs,
|
|
* unless you specifically block reads/writes to reg 0.
|
|
*/
|
|
cpu_gpr[0] = NULL;
|
|
|
|
for (i = 1; i < 32; i++) {
|
|
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
|
|
}
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
|
|
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
|
|
}
|
|
|
|
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
|
|
cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
|
|
load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
|
|
"load_res");
|
|
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
|
|
"load_val");
|
|
#ifndef CONFIG_USER_ONLY
|
|
/* Assign PM CSRs to tcg globals */
|
|
pm_mask[PRV_U] =
|
|
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
|
|
pm_base[PRV_U] =
|
|
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
|
|
pm_mask[PRV_S] =
|
|
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
|
|
pm_base[PRV_S] =
|
|
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
|
|
pm_mask[PRV_M] =
|
|
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
|
|
pm_base[PRV_M] =
|
|
tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
|
|
#endif
|
|
}
|