0d1dcb0bb1
Power9 is supposed to have 4 PIB-connected I2C engines with the
following number of ports on each engine:
0: 2
1: 13
2: 2
3: 2
Power10 also has 4 engines but has the following number of ports
on each engine:
0: 14
1: 14
2: 2
3: 16
Current code assumes that they all have the same (maximum) number.
This can be a problem if software expects to see a certain number
of ports present (Power Hypervisor seems to care).
Fixed this by adding separate tables for power9 and power10 that
map the I2C controller number to the number of I2C buses that should
be attached for that engine.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Message-ID: <20231025152714.956664-1-milesg@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
#ifndef PPC_PNV_CHIP_H
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#define PPC_PNV_CHIP_H
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#include "hw/pci-host/pnv_phb4.h"
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#include "hw/ppc/pnv_core.h"
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#include "hw/ppc/pnv_homer.h"
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_occ.h"
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_sbe.h"
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#include "hw/ppc/pnv_xive.h"
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#include "hw/ppc/pnv_i2c.h"
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#include "hw/sysbus.h"
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OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
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PNV_CHIP)
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struct PnvChip {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t chip_id;
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uint64_t ram_start;
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uint64_t ram_size;
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uint32_t nr_cores;
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uint32_t nr_threads;
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uint64_t cores_mask;
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PnvCore **cores;
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uint32_t num_pecs;
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MemoryRegion xscom_mmio;
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MemoryRegion xscom;
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AddressSpace xscom_as;
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MemoryRegion *fw_mr;
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gchar *dt_isa_nodename;
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};
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#define TYPE_PNV8_CHIP "pnv8-chip"
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DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
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TYPE_PNV8_CHIP)
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struct Pnv8Chip {
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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MemoryRegion icp_mmio;
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PnvLpcController lpc;
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Pnv8Psi psi;
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PnvOCC occ;
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PnvHomer homer;
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#define PNV8_CHIP_PHB3_MAX 4
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/*
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* The array is used to allow quick access to the phbs by
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* pnv_ics_get_child() and pnv_ics_resend_child().
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*/
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PnvPHB *phbs[PNV8_CHIP_PHB3_MAX];
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uint32_t num_phbs;
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XICSFabric *xics;
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};
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#define TYPE_PNV9_CHIP "pnv9-chip"
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DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
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TYPE_PNV9_CHIP)
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struct Pnv9Chip {
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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PnvXive xive;
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvOCC occ;
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PnvSBE sbe;
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PnvHomer homer;
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uint32_t nr_quads;
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PnvQuad *quads;
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#define PNV9_CHIP_MAX_PEC 3
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PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
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#define PNV9_CHIP_MAX_I2C 4
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PnvI2C i2c[PNV9_CHIP_MAX_I2C];
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};
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/*
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* A SMT8 fused core is a pair of SMT4 cores.
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*/
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#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
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#define TYPE_PNV10_CHIP "pnv10-chip"
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DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
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TYPE_PNV10_CHIP)
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struct Pnv10Chip {
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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PnvXive2 xive;
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvOCC occ;
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PnvSBE sbe;
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PnvHomer homer;
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uint32_t nr_quads;
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PnvQuad *quads;
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#define PNV10_CHIP_MAX_PEC 2
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PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
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#define PNV10_CHIP_MAX_I2C 4
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PnvI2C i2c[PNV10_CHIP_MAX_I2C];
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};
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#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
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struct PnvChipClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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uint64_t chip_cfam_id;
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uint64_t cores_mask;
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uint32_t num_pecs;
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uint32_t num_phbs;
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uint32_t i2c_num_engines;
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const int *i2c_ports_per_engine;
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DeviceRealize parent_realize;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
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void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
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void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
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void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
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ISABus *(*isa_create)(PnvChip *chip, Error **errp);
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void (*dt_populate)(PnvChip *chip, void *fdt);
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void (*pic_print_info)(PnvChip *chip, Monitor *mon);
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uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
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uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
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};
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#endif
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