20303e42d4
Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
131 lines
3.0 KiB
ArmAsm
131 lines
3.0 KiB
ArmAsm
#include <core-isa.h>
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#if XTENSA_HAVE_BE
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OUTPUT_FORMAT("elf32-xtensa-be")
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#else
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OUTPUT_FORMAT("elf32-xtensa-le")
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#endif
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ENTRY(_start)
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__DYNAMIC = 0;
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MEMORY {
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ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000 /* 128M */
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rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000 /* 4k */
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}
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SECTIONS
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{
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.init :
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{
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*(.init)
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*(.init.*)
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} > rom
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.vector :
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{
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. = XCHAL_WINDOW_OF4_VECOFS;
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*(.vector.window_overflow_4)
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*(.vector.window_overflow_4.*)
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. = XCHAL_WINDOW_UF4_VECOFS;
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*(.vector.window_underflow_4)
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*(.vector.window_underflow_4.*)
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. = XCHAL_WINDOW_OF8_VECOFS;
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*(.vector.window_overflow_8)
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*(.vector.window_overflow_8.*)
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. = XCHAL_WINDOW_UF8_VECOFS;
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*(.vector.window_underflow_8)
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*(.vector.window_underflow_8.*)
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. = XCHAL_WINDOW_OF12_VECOFS;
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*(.vector.window_overflow_12)
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*(.vector.window_overflow_12.*)
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. = XCHAL_WINDOW_UF12_VECOFS;
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*(.vector.window_underflow_12)
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*(.vector.window_underflow_12.*)
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
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. = XCHAL_INTLEVEL2_VECOFS;
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*(.vector.level2)
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*(.vector.level2.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
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. = XCHAL_INTLEVEL3_VECOFS;
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*(.vector.level3)
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*(.vector.level3.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
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. = XCHAL_INTLEVEL4_VECOFS;
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*(.vector.level4)
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*(.vector.level4.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
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. = XCHAL_INTLEVEL5_VECOFS;
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*(.vector.level5)
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*(.vector.level5.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
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. = XCHAL_INTLEVEL6_VECOFS;
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*(.vector.level6)
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*(.vector.level6.*)
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
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. = XCHAL_INTLEVEL7_VECOFS;
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*(.vector.level7)
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*(.vector.level7.*)
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#endif
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. = XCHAL_KERNEL_VECOFS;
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*(.vector.kernel)
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*(.vector.kernel.*)
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. = XCHAL_USER_VECOFS;
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*(.vector.user)
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*(.vector.user.*)
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. = XCHAL_DOUBLEEXC_VECOFS;
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*(.vector.double)
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*(.vector.double.*)
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} > ram
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.text :
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{
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_ftext = .;
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*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
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_etext = .;
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} > ram
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.rodata :
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{
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. = ALIGN(4);
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_frodata = .;
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.rodata1)
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_erodata = .;
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} > ram
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.data :
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{
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. = ALIGN(4);
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_fdata = .;
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*(.data .data.* .gnu.linkonce.d.*)
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*(.data1)
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_gp = ALIGN(16);
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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_edata = .;
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} > ram
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.bss :
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{
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. = ALIGN(4);
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_fbss = .;
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*(.dynsbss)
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(.scommon)
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*(.dynbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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*(COMMON)
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_ebss = .;
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_end = .;
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} > ram
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}
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PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16);
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