650 lines
20 KiB
C
650 lines
20 KiB
C
/*
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* QEMU PowerPC 405 evaluation boards emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "ppc.h"
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#include "ppc405.h"
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#include "nvram.h"
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#include "flash.h"
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#include "sysemu.h"
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#include "block.h"
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#include "boards.h"
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#include "qemu-log.h"
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#include "loader.h"
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#define BIOS_FILENAME "ppc405_rom.bin"
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#define BIOS_SIZE (2048 * 1024)
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#define KERNEL_LOAD_ADDR 0x00000000
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#define INITRD_LOAD_ADDR 0x01800000
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#define USE_FLASH_BIOS
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#define DEBUG_BOARD_INIT
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/*****************************************************************************/
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/* PPC405EP reference board (IBM) */
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/* Standalone board with:
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* - PowerPC 405EP CPU
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* - SDRAM (0x00000000)
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* - Flash (0xFFF80000)
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* - SRAM (0xFFF00000)
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* - NVRAM (0xF0000000)
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* - FPGA (0xF0300000)
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*/
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typedef struct ref405ep_fpga_t ref405ep_fpga_t;
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struct ref405ep_fpga_t {
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uint8_t reg0;
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uint8_t reg1;
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};
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static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
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{
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ref405ep_fpga_t *fpga;
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uint32_t ret;
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fpga = opaque;
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switch (addr) {
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case 0x0:
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ret = fpga->reg0;
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break;
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case 0x1:
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ret = fpga->reg1;
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break;
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default:
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ret = 0;
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break;
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}
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return ret;
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}
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static void ref405ep_fpga_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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ref405ep_fpga_t *fpga;
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fpga = opaque;
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switch (addr) {
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case 0x0:
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/* Read only */
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break;
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case 0x1:
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fpga->reg1 = value;
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break;
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default:
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break;
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}
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}
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static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret;
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ret = ref405ep_fpga_readb(opaque, addr) << 8;
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ret |= ref405ep_fpga_readb(opaque, addr + 1);
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return ret;
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}
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static void ref405ep_fpga_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
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ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
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}
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static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret;
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ret = ref405ep_fpga_readb(opaque, addr) << 24;
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ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
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ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
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ret |= ref405ep_fpga_readb(opaque, addr + 3);
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return ret;
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}
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static void ref405ep_fpga_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
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ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
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ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
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ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
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}
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static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
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&ref405ep_fpga_readb,
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&ref405ep_fpga_readw,
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&ref405ep_fpga_readl,
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};
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static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
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&ref405ep_fpga_writeb,
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&ref405ep_fpga_writew,
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&ref405ep_fpga_writel,
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};
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static void ref405ep_fpga_reset (void *opaque)
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{
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ref405ep_fpga_t *fpga;
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fpga = opaque;
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fpga->reg0 = 0x00;
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fpga->reg1 = 0x0F;
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}
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static void ref405ep_fpga_init (uint32_t base)
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{
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ref405ep_fpga_t *fpga;
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int fpga_memory;
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fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
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fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
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ref405ep_fpga_write, fpga);
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cpu_register_physical_memory(base, 0x00000100, fpga_memory);
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qemu_register_reset(&ref405ep_fpga_reset, fpga);
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}
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static void ref405ep_init (ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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{
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char *filename;
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ppc4xx_bd_info_t bd;
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CPUPPCState *env;
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qemu_irq *pic;
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ram_addr_t sram_offset, bios_offset, bdloc;
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target_phys_addr_t ram_bases[2], ram_sizes[2];
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target_ulong sram_size, bios_size;
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//int phy_addr = 0;
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//static int phy_addr = 1;
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target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
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int linux_boot;
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int fl_idx, fl_sectors, len;
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int ppc_boot_device = boot_device[0];
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DriveInfo *dinfo;
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/* XXX: fix this */
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ram_bases[0] = qemu_ram_alloc(0x08000000);
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ram_sizes[0] = 0x08000000;
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ram_bases[1] = 0x00000000;
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ram_sizes[1] = 0x00000000;
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ram_size = 128 * 1024 * 1024;
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register cpu\n", __func__);
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#endif
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env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
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kernel_filename == NULL ? 0 : 1);
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/* allocate SRAM */
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sram_size = 512 * 1024;
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sram_offset = qemu_ram_alloc(sram_size);
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
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#endif
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cpu_register_physical_memory(0xFFF00000, sram_size,
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sram_offset | IO_MEM_RAM);
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/* allocate and load BIOS */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register BIOS\n", __func__);
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#endif
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fl_idx = 0;
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#ifdef USE_FLASH_BIOS
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dinfo = drive_get(IF_PFLASH, 0, fl_idx);
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if (dinfo) {
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bios_size = bdrv_getlength(dinfo->bdrv);
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bios_offset = qemu_ram_alloc(bios_size);
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fl_sectors = (bios_size + 65535) >> 16;
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#ifdef DEBUG_BOARD_INIT
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printf("Register parallel flash %d size " TARGET_FMT_lx
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" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
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fl_idx, bios_size, bios_offset, -bios_size,
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bdrv_get_device_name(dinfo->bdrv), fl_sectors);
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#endif
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pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
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dinfo->bdrv, 65536, fl_sectors, 1,
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2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
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fl_idx++;
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} else
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#endif
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{
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#ifdef DEBUG_BOARD_INIT
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printf("Load BIOS from file\n");
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#endif
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bios_offset = qemu_ram_alloc(BIOS_SIZE);
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (filename) {
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bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
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qemu_free(filename);
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} else {
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bios_size = -1;
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}
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
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bios_name);
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exit(1);
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}
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bios_size = (bios_size + 0xfff) & ~0xfff;
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cpu_register_physical_memory((uint32_t)(-bios_size),
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bios_size, bios_offset | IO_MEM_ROM);
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}
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/* Register FPGA */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register FPGA\n", __func__);
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#endif
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ref405ep_fpga_init(0xF0300000);
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/* Register NVRAM */
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#ifdef DEBUG_BOARD_INIT
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printf("%s: register NVRAM\n", __func__);
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#endif
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m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
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/* Load kernel */
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linux_boot = (kernel_filename != NULL);
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if (linux_boot) {
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#ifdef DEBUG_BOARD_INIT
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printf("%s: load kernel\n", __func__);
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#endif
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memset(&bd, 0, sizeof(bd));
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bd.bi_memstart = 0x00000000;
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bd.bi_memsize = ram_size;
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bd.bi_flashstart = -bios_size;
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bd.bi_flashsize = -bios_size;
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bd.bi_flashoffset = 0;
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bd.bi_sramstart = 0xFFF00000;
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bd.bi_sramsize = sram_size;
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bd.bi_bootflags = 0;
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bd.bi_intfreq = 133333333;
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bd.bi_busfreq = 33333333;
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bd.bi_baudrate = 115200;
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bd.bi_s_version[0] = 'Q';
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bd.bi_s_version[1] = 'M';
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bd.bi_s_version[2] = 'U';
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bd.bi_s_version[3] = '\0';
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bd.bi_r_version[0] = 'Q';
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bd.bi_r_version[1] = 'E';
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bd.bi_r_version[2] = 'M';
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bd.bi_r_version[3] = 'U';
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bd.bi_r_version[4] = '\0';
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bd.bi_procfreq = 133333333;
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bd.bi_plb_busfreq = 33333333;
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bd.bi_pci_busfreq = 33333333;
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bd.bi_opbfreq = 33333333;
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bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
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env->gpr[3] = bdloc;
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kernel_base = KERNEL_LOAD_ADDR;
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/* now we can load the kernel */
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kernel_size = load_image_targphys(kernel_filename, kernel_base,
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ram_size - kernel_base);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
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kernel_size, kernel_base);
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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env->gpr[4] = initrd_base;
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env->gpr[5] = initrd_size;
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ppc_boot_device = 'm';
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if (kernel_cmdline != NULL) {
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len = strlen(kernel_cmdline);
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bdloc -= ((len + 255) & ~255);
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cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
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env->gpr[6] = bdloc;
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env->gpr[7] = bdloc + len;
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} else {
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env->gpr[6] = 0;
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env->gpr[7] = 0;
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}
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env->nip = KERNEL_LOAD_ADDR;
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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bdloc = 0;
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}
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#ifdef DEBUG_BOARD_INIT
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printf("%s: Done\n", __func__);
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#endif
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printf("bdloc %016lx\n", (unsigned long)bdloc);
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}
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static QEMUMachine ref405ep_machine = {
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.name = "ref405ep",
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.desc = "ref405ep",
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.init = ref405ep_init,
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};
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/*****************************************************************************/
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/* AMCC Taihu evaluation board */
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/* - PowerPC 405EP processor
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* - SDRAM 128 MB at 0x00000000
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* - Boot flash 2 MB at 0xFFE00000
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* - Application flash 32 MB at 0xFC000000
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* - 2 serial ports
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* - 2 ethernet PHY
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* - 1 USB 1.1 device 0x50000000
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* - 1 LCD display 0x50100000
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* - 1 CPLD 0x50100000
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* - 1 I2C EEPROM
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* - 1 I2C thermal sensor
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* - a set of LEDs
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* - bit-bang SPI port using GPIOs
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* - 1 EBC interface connector 0 0x50200000
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* - 1 cardbus controller + expansion slot.
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* - 1 PCI expansion slot.
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*/
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typedef struct taihu_cpld_t taihu_cpld_t;
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struct taihu_cpld_t {
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uint8_t reg0;
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uint8_t reg1;
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};
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static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
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{
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taihu_cpld_t *cpld;
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uint32_t ret;
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cpld = opaque;
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switch (addr) {
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case 0x0:
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ret = cpld->reg0;
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break;
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case 0x1:
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ret = cpld->reg1;
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break;
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default:
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ret = 0;
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break;
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}
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return ret;
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}
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static void taihu_cpld_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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taihu_cpld_t *cpld;
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cpld = opaque;
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switch (addr) {
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case 0x0:
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/* Read only */
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break;
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case 0x1:
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cpld->reg1 = value;
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break;
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default:
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break;
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}
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}
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static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret;
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ret = taihu_cpld_readb(opaque, addr) << 8;
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ret |= taihu_cpld_readb(opaque, addr + 1);
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return ret;
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}
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static void taihu_cpld_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
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taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
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}
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static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret;
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ret = taihu_cpld_readb(opaque, addr) << 24;
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ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
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ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
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ret |= taihu_cpld_readb(opaque, addr + 3);
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return ret;
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}
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static void taihu_cpld_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
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taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
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taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
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taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
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}
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static CPUReadMemoryFunc * const taihu_cpld_read[] = {
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&taihu_cpld_readb,
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&taihu_cpld_readw,
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&taihu_cpld_readl,
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};
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static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
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&taihu_cpld_writeb,
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&taihu_cpld_writew,
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&taihu_cpld_writel,
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};
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static void taihu_cpld_reset (void *opaque)
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{
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taihu_cpld_t *cpld;
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cpld = opaque;
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cpld->reg0 = 0x01;
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cpld->reg1 = 0x80;
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}
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static void taihu_cpld_init (uint32_t base)
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{
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taihu_cpld_t *cpld;
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int cpld_memory;
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cpld = qemu_mallocz(sizeof(taihu_cpld_t));
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cpld_memory = cpu_register_io_memory(taihu_cpld_read,
|
|
taihu_cpld_write, cpld);
|
|
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
|
|
qemu_register_reset(&taihu_cpld_reset, cpld);
|
|
}
|
|
|
|
static void taihu_405ep_init(ram_addr_t ram_size,
|
|
const char *boot_device,
|
|
const char *kernel_filename,
|
|
const char *kernel_cmdline,
|
|
const char *initrd_filename,
|
|
const char *cpu_model)
|
|
{
|
|
char *filename;
|
|
CPUPPCState *env;
|
|
qemu_irq *pic;
|
|
ram_addr_t bios_offset;
|
|
target_phys_addr_t ram_bases[2], ram_sizes[2];
|
|
target_ulong bios_size;
|
|
target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
|
|
int linux_boot;
|
|
int fl_idx, fl_sectors;
|
|
int ppc_boot_device = boot_device[0];
|
|
DriveInfo *dinfo;
|
|
|
|
/* RAM is soldered to the board so the size cannot be changed */
|
|
ram_bases[0] = qemu_ram_alloc(0x04000000);
|
|
ram_sizes[0] = 0x04000000;
|
|
ram_bases[1] = qemu_ram_alloc(0x04000000);
|
|
ram_sizes[1] = 0x04000000;
|
|
ram_size = 0x08000000;
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("%s: register cpu\n", __func__);
|
|
#endif
|
|
env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
|
|
kernel_filename == NULL ? 0 : 1);
|
|
/* allocate and load BIOS */
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("%s: register BIOS\n", __func__);
|
|
#endif
|
|
fl_idx = 0;
|
|
#if defined(USE_FLASH_BIOS)
|
|
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
|
|
if (dinfo) {
|
|
bios_size = bdrv_getlength(dinfo->bdrv);
|
|
/* XXX: should check that size is 2MB */
|
|
// bios_size = 2 * 1024 * 1024;
|
|
fl_sectors = (bios_size + 65535) >> 16;
|
|
bios_offset = qemu_ram_alloc(bios_size);
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("Register parallel flash %d size " TARGET_FMT_lx
|
|
" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
|
|
fl_idx, bios_size, bios_offset, -bios_size,
|
|
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
|
|
#endif
|
|
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
|
|
dinfo->bdrv, 65536, fl_sectors, 1,
|
|
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
|
|
fl_idx++;
|
|
} else
|
|
#endif
|
|
{
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("Load BIOS from file\n");
|
|
#endif
|
|
if (bios_name == NULL)
|
|
bios_name = BIOS_FILENAME;
|
|
bios_offset = qemu_ram_alloc(BIOS_SIZE);
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
if (filename) {
|
|
bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
|
|
} else {
|
|
bios_size = -1;
|
|
}
|
|
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
|
fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
|
|
bios_name);
|
|
exit(1);
|
|
}
|
|
bios_size = (bios_size + 0xfff) & ~0xfff;
|
|
cpu_register_physical_memory((uint32_t)(-bios_size),
|
|
bios_size, bios_offset | IO_MEM_ROM);
|
|
}
|
|
/* Register Linux flash */
|
|
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
|
|
if (dinfo) {
|
|
bios_size = bdrv_getlength(dinfo->bdrv);
|
|
/* XXX: should check that size is 32MB */
|
|
bios_size = 32 * 1024 * 1024;
|
|
fl_sectors = (bios_size + 65535) >> 16;
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("Register parallel flash %d size " TARGET_FMT_lx
|
|
" at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
|
|
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
|
|
bdrv_get_device_name(dinfo->bdrv));
|
|
#endif
|
|
bios_offset = qemu_ram_alloc(bios_size);
|
|
pflash_cfi02_register(0xfc000000, bios_offset,
|
|
dinfo->bdrv, 65536, fl_sectors, 1,
|
|
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
|
|
fl_idx++;
|
|
}
|
|
/* Register CLPD & LCD display */
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("%s: register CPLD\n", __func__);
|
|
#endif
|
|
taihu_cpld_init(0x50100000);
|
|
/* Load kernel */
|
|
linux_boot = (kernel_filename != NULL);
|
|
if (linux_boot) {
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("%s: load kernel\n", __func__);
|
|
#endif
|
|
kernel_base = KERNEL_LOAD_ADDR;
|
|
/* now we can load the kernel */
|
|
kernel_size = load_image_targphys(kernel_filename, kernel_base,
|
|
ram_size - kernel_base);
|
|
if (kernel_size < 0) {
|
|
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
|
kernel_filename);
|
|
exit(1);
|
|
}
|
|
/* load initrd */
|
|
if (initrd_filename) {
|
|
initrd_base = INITRD_LOAD_ADDR;
|
|
initrd_size = load_image_targphys(initrd_filename, initrd_base,
|
|
ram_size - initrd_base);
|
|
if (initrd_size < 0) {
|
|
fprintf(stderr,
|
|
"qemu: could not load initial ram disk '%s'\n",
|
|
initrd_filename);
|
|
exit(1);
|
|
}
|
|
} else {
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
}
|
|
ppc_boot_device = 'm';
|
|
} else {
|
|
kernel_base = 0;
|
|
kernel_size = 0;
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
}
|
|
#ifdef DEBUG_BOARD_INIT
|
|
printf("%s: Done\n", __func__);
|
|
#endif
|
|
}
|
|
|
|
static QEMUMachine taihu_machine = {
|
|
.name = "taihu",
|
|
.desc = "taihu",
|
|
.init = taihu_405ep_init,
|
|
};
|
|
|
|
static void ppc405_machine_init(void)
|
|
{
|
|
qemu_register_machine(&ref405ep_machine);
|
|
qemu_register_machine(&taihu_machine);
|
|
}
|
|
|
|
machine_init(ppc405_machine_init);
|