qemu-e2k/target/riscv/insn_trans
Alistair Francis 0736febb2d
target/riscv: Remove the hret instruction
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-27 13:45:45 -08:00
..
trans_privileged.inc.c target/riscv: Remove the hret instruction 2020-02-27 13:45:45 -08:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
trans_rvd.inc.c target/riscv: fsd/fsw doesn't dirty FP state 2020-01-16 10:03:08 -08:00
trans_rvf.inc.c target/riscv: fsd/fsw doesn't dirty FP state 2020-01-16 10:03:08 -08:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-22 00:26:39 -07:00