617564bf92
The Flex Bus Port DVSEC was missing on type 3 devices which was blocking RAS checks.[1] Add the Flex Bus Port DVSEC to type 3 devices as per CXL 3.0 8.2.1.3. [1] https://lore.kernel.org/linux-cxl/167096738875.2861540.11815053323626849940.stgit@djiang5-desk3.ch.intel.com/ Cc: Dave Jiang <dave.jiang@intel.com> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Ben Widawsky <bwidawsk@kernel.org> Cc: qemu-devel@nongnu.org Cc: linux-cxl@vger.kernel.org Signed-off-by: Ira Weiny <ira.weiny@intel.com> Message-Id: <20221213-ira-flexbus-port-v2-1-eaa48d0e0700@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> |
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| .. | ||
| Kconfig | ||
| cxl_type3.c | ||
| memory-device.c | ||
| meson.build | ||
| npcm7xx_mc.c | ||
| nvdimm.c | ||
| pc-dimm.c | ||
| sparse-mem.c | ||
| trace-events | ||
| trace.h | ||