qemu-e2k/target
Peter Maydell 052e6534c4 First RISC-V PR for QEMU 8.0
* Fix PMP propagation for tlb
 * Collection of bug fixes
 * Bump the OpenTitan supported version
 * Add smstateen support
 * Support native debug icount trigger
 * Remove the redundant ipi-id property in the virt machine
 * Support cache-related PMU events in virtual mode
 * Add some missing PolarFire SoC io regions
 * Fix mret exception cause when no pmp rule is configured
 * Fix bug where disabling compressed instructions would crash QEMU
 * Add Zawrs ISA extension support
 * A range of code refactoring and cleanups
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Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 8.0

* Fix PMP propagation for tlb
* Collection of bug fixes
* Bump the OpenTitan supported version
* Add smstateen support
* Support native debug icount trigger
* Remove the redundant ipi-id property in the virt machine
* Support cache-related PMU events in virtual mode
* Add some missing PolarFire SoC io regions
* Fix mret exception cause when no pmp rule is configured
* Fix bug where disabling compressed instructions would crash QEMU
* Add Zawrs ISA extension support
* A range of code refactoring and cleanups

# gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits)
  hw/intc: sifive_plic: Fix the pending register range check
  hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
  hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
  hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
  hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
  hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
  hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
  hw/intc: sifive_plic: Update "num-sources" property default value
  hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize()
  hw/intc: sifive_plic: Improve robustness of the PLIC config parser
  hw/intc: sifive_plic: Drop PLICMode_H
  hw/riscv: spike: Remove misleading comments
  hw/riscv: Sort machines Kconfig options in alphabetical order
  hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
  hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
  hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
  RISC-V: Add Zawrs ISA extension support
  target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
  target/riscv: Simplify helper_sret() a little bit
  target/riscv: Set pc_succ_insn for !rvc illegal insn
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-06 22:15:53 +00:00
..
alpha accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
arm target/arm: align exposed ID registers with Linux 2023-01-05 14:12:34 +00:00
avr target/avr: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
cris target/cris: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
hexagon Hexagon (target/hexagon) implement mutability mask for GPRs 2023-01-05 09:19:02 -08:00
hppa target/hppa: Fix fid instruction emulation 2022-12-19 23:14:06 +01:00
i386 target/i386: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
loongarch target/loongarch: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
m68k target/m68k: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
microblaze target/microblaze: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
mips target/mips: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
nios2 target/nios2: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
openrisc target/openrisc: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
ppc target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_interrupt_exittb 2023-01-04 16:20:01 -08:00
riscv First RISC-V PR for QEMU 8.0 2023-01-06 22:15:53 +00:00
rx target/rx: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
s390x target/s390x: The MVCP and MVCS instructions are not privileged 2022-12-15 15:02:34 +01:00
sh4 target/sh4: Mask restore of env->flags from tb->flags 2022-12-18 09:36:07 -08:00
sparc target/sparc: Avoid TCGV_{LOW,HIGH} 2023-01-05 11:41:28 -08:00
tricore target/tricore: Fix gdbstub write to address registers 2022-12-18 09:39:17 -08:00
xtensa target/xtensa: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00