f5fba9d27f
The compatible string is changed to fsl,mpic on all e500 platforms, to advertise the existence of BRR1. This matches what the device tree will have on real hardware. With MPIC v4.2 max_cpu can be increased from 15 to 32. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
26 lines
595 B
C
26 lines
595 B
C
#ifndef PPCE500_H
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#define PPCE500_H
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typedef struct PPCE500Params {
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/* Standard QEMU machine init params */
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ram_addr_t ram_size;
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const char *boot_device;
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const char *kernel_filename;
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const char *kernel_cmdline;
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const char *initrd_filename;
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const char *cpu_model;
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int pci_first_slot;
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int pci_nr_slots;
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/* e500-specific params */
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/* required -- must at least add toplevel board compatible */
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void (*fixup_devtree)(struct PPCE500Params *params, void *fdt);
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int mpic_version;
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} PPCE500Params;
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void ppce500_init(PPCE500Params *params);
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#endif
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