4ea5fe997d
These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>
379 lines
11 KiB
C
379 lines
11 KiB
C
/*
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* ARM gdb server stub: AArch64 specific functions.
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*
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "internals.h"
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#include "gdbstub/helpers.h"
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int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (n < 31) {
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/* Core integer register. */
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return gdb_get_reg64(mem_buf, env->xregs[n]);
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}
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switch (n) {
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case 31:
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return gdb_get_reg64(mem_buf, env->xregs[31]);
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case 32:
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return gdb_get_reg64(mem_buf, env->pc);
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case 33:
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return gdb_get_reg32(mem_buf, pstate_read(env));
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}
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/* Unknown register. */
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return 0;
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}
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int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint64_t tmp;
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tmp = ldq_p(mem_buf);
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if (n < 31) {
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/* Core integer register. */
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env->xregs[n] = tmp;
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return 8;
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}
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switch (n) {
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case 31:
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env->xregs[31] = tmp;
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return 8;
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case 32:
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env->pc = tmp;
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return 8;
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case 33:
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/* CPSR */
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pstate_write(env, tmp);
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return 4;
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}
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/* Unknown register. */
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return 0;
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}
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int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
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{
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switch (reg) {
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case 0 ... 31:
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{
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/* 128 bit FP register - quads are in LE order */
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uint64_t *q = aa64_vfp_qreg(env, reg);
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return gdb_get_reg128(buf, q[1], q[0]);
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}
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case 32:
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/* FPSR */
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return gdb_get_reg32(buf, vfp_get_fpsr(env));
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case 33:
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/* FPCR */
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return gdb_get_reg32(buf, vfp_get_fpcr(env));
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default:
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return 0;
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}
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}
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int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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switch (reg) {
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case 0 ... 31:
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/* 128 bit FP register */
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{
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uint64_t *q = aa64_vfp_qreg(env, reg);
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q[0] = ldq_le_p(buf);
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q[1] = ldq_le_p(buf + 8);
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return 16;
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}
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case 32:
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/* FPSR */
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vfp_set_fpsr(env, ldl_p(buf));
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return 4;
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case 33:
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/* FPCR */
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vfp_set_fpcr(env, ldl_p(buf));
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return 4;
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default:
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return 0;
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}
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}
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int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
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{
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ARMCPU *cpu = env_archcpu(env);
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switch (reg) {
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/* The first 32 registers are the zregs */
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case 0 ... 31:
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{
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int vq, len = 0;
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for (vq = 0; vq < cpu->sve_max_vq; vq++) {
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len += gdb_get_reg128(buf,
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env->vfp.zregs[reg].d[vq * 2 + 1],
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env->vfp.zregs[reg].d[vq * 2]);
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}
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return len;
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}
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case 32:
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return gdb_get_reg32(buf, vfp_get_fpsr(env));
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case 33:
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return gdb_get_reg32(buf, vfp_get_fpcr(env));
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/* then 16 predicates and the ffr */
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case 34 ... 50:
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{
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int preg = reg - 34;
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int vq, len = 0;
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for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
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len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
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}
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return len;
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}
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case 51:
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{
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/*
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* We report in Vector Granules (VG) which is 64bit in a Z reg
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* while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
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*/
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int vq = sve_vqm1_for_el(env, arm_current_el(env)) + 1;
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return gdb_get_reg64(buf, vq * 2);
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}
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default:
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/* gdbstub asked for something out our range */
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qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
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break;
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}
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return 0;
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}
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int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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ARMCPU *cpu = env_archcpu(env);
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/* The first 32 registers are the zregs */
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switch (reg) {
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/* The first 32 registers are the zregs */
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case 0 ... 31:
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{
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int vq, len = 0;
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uint64_t *p = (uint64_t *) buf;
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for (vq = 0; vq < cpu->sve_max_vq; vq++) {
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env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
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env->vfp.zregs[reg].d[vq * 2] = *p++;
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len += 16;
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}
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return len;
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}
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case 32:
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vfp_set_fpsr(env, *(uint32_t *)buf);
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return 4;
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case 33:
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vfp_set_fpcr(env, *(uint32_t *)buf);
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return 4;
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case 34 ... 50:
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{
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int preg = reg - 34;
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int vq, len = 0;
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uint64_t *p = (uint64_t *) buf;
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for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
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env->vfp.pregs[preg].p[vq / 4] = *p++;
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len += 8;
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}
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return len;
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}
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case 51:
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/* cannot set vg via gdbstub */
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return 0;
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default:
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/* gdbstub asked for something out our range */
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break;
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}
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return 0;
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}
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int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
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{
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switch (reg) {
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case 0: /* pauth_dmask */
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case 1: /* pauth_cmask */
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case 2: /* pauth_dmask_high */
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case 3: /* pauth_cmask_high */
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/*
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* Note that older versions of this feature only contained
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* pauth_{d,c}mask, for use with Linux user processes, and
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* thus exclusively in the low half of the address space.
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*
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* To support system mode, and to debug kernels, two new regs
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* were added to cover the high half of the address space.
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* For the purpose of pauth_ptr_mask, we can use any well-formed
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* address within the address space half -- here, 0 and -1.
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*/
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{
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bool is_data = !(reg & 1);
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bool is_high = reg & 2;
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uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
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return gdb_get_reg64(buf, mask);
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}
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default:
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return 0;
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}
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}
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int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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/* All pseudo registers are read-only. */
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return 0;
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}
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static void output_vector_union_type(GString *s, int reg_width,
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const char *name)
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{
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struct TypeSize {
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const char *gdb_type;
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short size;
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char sz, suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", 128, 'q', 'u' },
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{ "int128", 128, 'q', 's' },
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/* 64 bit */
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{ "ieee_double", 64, 'd', 'f' },
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{ "uint64", 64, 'd', 'u' },
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{ "int64", 64, 'd', 's' },
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/* 32 bit */
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{ "ieee_single", 32, 's', 'f' },
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{ "uint32", 32, 's', 'u' },
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{ "int32", 32, 's', 's' },
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/* 16 bit */
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{ "ieee_half", 16, 'h', 'f' },
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{ "uint16", 16, 'h', 'u' },
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{ "int16", 16, 'h', 's' },
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/* bytes */
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{ "uint8", 8, 'b', 'u' },
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{ "int8", 8, 'b', 's' },
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};
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static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
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int i, j;
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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g_string_append_printf(s,
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"<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
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name, vec_lanes[i].sz, vec_lanes[i].suffix,
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vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
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}
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/*
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* Now define a union for each size group containing unsigned and
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* signed and potentially float versions of each size from 128 to
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* 8 bits.
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*/
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for (i = 0; i < ARRAY_SIZE(suf); i++) {
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int bits = 8 << i;
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g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
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for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
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if (vec_lanes[j].size == bits) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
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vec_lanes[j].suffix, name,
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vec_lanes[j].sz, vec_lanes[j].suffix);
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}
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}
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g_string_append(s, "</union>");
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}
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/* And now the final union of unions */
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g_string_append_printf(s, "<union id=\"%s\">", name);
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for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
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suf[i], name, suf[i]);
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}
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g_string_append(s, "</union>");
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}
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int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
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int reg_width = cpu->sve_max_vq * 128;
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int pred_width = cpu->sve_max_vq * 16;
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int base_reg = orig_base_reg;
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int i;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
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/* Create the vector union type. */
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output_vector_union_type(s, reg_width, "svev");
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/* Create the predicate vector type. */
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g_string_append_printf(s,
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"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
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pred_width / 8);
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/* Define the vector registers. */
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for (i = 0; i < 32; i++) {
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g_string_append_printf(s,
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"<reg name=\"z%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svev\"/>",
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i, reg_width, base_reg++);
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}
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/* fpscr & status registers */
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g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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/* Define the predicate registers. */
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for (i = 0; i < 16; i++) {
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g_string_append_printf(s,
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"<reg name=\"p%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svep\"/>",
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i, pred_width, base_reg++);
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}
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g_string_append_printf(s,
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"<reg name=\"ffr\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"svep\"/>",
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pred_width, base_reg++);
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/* Define the vector length pseudo-register. */
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g_string_append_printf(s,
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"<reg name=\"vg\" bitsize=\"64\""
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" regnum=\"%d\" type=\"int\"/>",
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base_reg++);
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g_string_append_printf(s, "</feature>");
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info->desc = g_string_free(s, false);
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info->num = base_reg - orig_base_reg;
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return info->num;
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}
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