33f21e4f04
In some cases, the guest can observe the wrong ordering of UIP and
interrupts. This can happen if the VCPU exit is timed like this:
iothread VCPU
... wait for interrupt ...
t-100ns read register A
t wake up, take BQL
t+100ns update_in_progress
return false
return UIP=0
trigger interrupt
The interrupt is late; the VCPU expected the falling edge of UIP to
happen after the interrupt. update_in_progress is already trying to
cover this case by latching UIP if the timer is going to fire soon,
and the fix is documented in the commit message for commit
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a9gtimer.c | ||
allwinner-a10-pit.c | ||
altera_timer.c | ||
arm_mptimer.c | ||
arm_timer.c | ||
armv7m_systick.c | ||
aspeed_timer.c | ||
cadence_ttc.c | ||
cmsdk-apb-timer.c | ||
digic-timer.c | ||
ds1338.c | ||
etraxfs_timer.c | ||
exynos4210_mct.c | ||
exynos4210_pwm.c | ||
exynos4210_rtc.c | ||
grlib_gptimer.c | ||
hpet.c | ||
i8254_common.c | ||
i8254.c | ||
imx_epit.c | ||
imx_gpt.c | ||
lm32_timer.c | ||
m48t59-internal.h | ||
m48t59-isa.c | ||
m48t59.c | ||
Makefile.objs | ||
mc146818rtc.c | ||
milkymist-sysctl.c | ||
mips_gictimer.c | ||
omap_gptimer.c | ||
omap_synctimer.c | ||
pl031.c | ||
puv3_ost.c | ||
pxa2xx_timer.c | ||
sh_timer.c | ||
slavio_timer.c | ||
stm32f2xx_timer.c | ||
sun4v-rtc.c | ||
trace-events | ||
twl92230.c | ||
xilinx_timer.c |