qemu-e2k/target-arm
Peter Crosthwaite f7838b5290 arm: cortex-a9: Fix cache-line size and associativity
For A9, The cache associativity is 4 and the lines size is 32B.
Self identify in CCSIDR accordingly. Cache size remains at 16k.

QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19 19:02:40 +01:00
..
arm_ldst.h
arm-semi.c
cpu64.c target-arm: Adjust debug ID registers per-CPU 2014-08-19 19:02:03 +01:00
cpu-qom.h target-arm: Adjust debug ID registers per-CPU 2014-08-19 19:02:03 +01:00
cpu.c arm: cortex-a9: Fix cache-line size and associativity 2014-08-19 19:02:40 +01:00
cpu.h target-arm: Implement ARMv8 single-stepping for AArch32 code 2014-08-19 19:02:03 +01:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper.c target-arm: Implement MDSCR_EL1 as having state 2014-08-19 19:02:03 +01:00
helper.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
internals.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 2014-08-19 19:02:25 +01:00
kvm-stub.c
kvm.c
machine.c
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
translate-a64.c target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
translate.c target-arm: Implement ARMv8 single-stepping for AArch32 code 2014-08-19 19:02:03 +01:00
translate.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00