241 lines
6.4 KiB
C
241 lines
6.4 KiB
C
/*
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* QEMU Sparc SLAVIO aux io port emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/* debug misc */
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//#define DEBUG_MISC
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/*
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* This is the auxio port, chip control and system control part of
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* chip STP2001 (Slave I/O), also produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* This also includes the PMC CPU idle controller.
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*/
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#ifdef DEBUG_MISC
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#define MISC_DPRINTF(fmt, args...) \
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do { printf("MISC: " fmt , ##args); } while (0)
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#else
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#define MISC_DPRINTF(fmt, args...)
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#endif
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typedef struct MiscState {
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int irq;
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uint8_t config;
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uint8_t aux1, aux2;
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uint8_t diag, mctrl;
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} MiscState;
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#define MISC_MAXADDR 1
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static void slavio_misc_update_irq(void *opaque)
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{
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MiscState *s = opaque;
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if ((s->aux2 & 0x4) && (s->config & 0x8)) {
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pic_set_irq(s->irq, 1);
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} else {
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pic_set_irq(s->irq, 0);
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}
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}
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static void slavio_misc_reset(void *opaque)
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{
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MiscState *s = opaque;
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// Diagnostic register not cleared in reset
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s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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}
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void slavio_set_power_fail(void *opaque, int power_failing)
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{
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MiscState *s = opaque;
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MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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if (power_failing && (s->config & 0x8)) {
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s->aux2 |= 0x4;
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} else {
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s->aux2 &= ~0x4;
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}
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slavio_misc_update_irq(s);
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}
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static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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MiscState *s = opaque;
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switch (addr & 0xfff0000) {
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case 0x1800000:
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MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
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s->config = val & 0xff;
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slavio_misc_update_irq(s);
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break;
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case 0x1900000:
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MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
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s->aux1 = val & 0xff;
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break;
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case 0x1910000:
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val &= 0x3;
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MISC_DPRINTF("Write aux2 %2.2x\n", val);
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val |= s->aux2 & 0x4;
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if (val & 0x2) // Clear Power Fail int
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val &= 0x1;
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s->aux2 = val;
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if (val & 1)
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qemu_system_shutdown_request();
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slavio_misc_update_irq(s);
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break;
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case 0x1a00000:
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MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
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s->diag = val & 0xff;
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break;
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case 0x1b00000:
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MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
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s->mctrl = val & 0xff;
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break;
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case 0x1f00000:
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MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
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if (val & 1)
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qemu_system_reset_request();
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break;
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case 0xa000000:
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MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
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#if 0
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// XXX: halting CPU does not work
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raise_exception(EXCP_HLT);
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cpu_loop_exit();
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#endif
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break;
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}
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}
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static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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switch (addr & 0xfff0000) {
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case 0x1800000:
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ret = s->config;
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MISC_DPRINTF("Read config %2.2x\n", ret);
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break;
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case 0x1900000:
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ret = s->aux1;
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MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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break;
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case 0x1910000:
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ret = s->aux2;
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MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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break;
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case 0x1a00000:
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ret = s->diag;
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MISC_DPRINTF("Read diag %2.2x\n", ret);
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break;
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case 0x1b00000:
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ret = s->mctrl;
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MISC_DPRINTF("Read modem control %2.2x\n", ret);
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break;
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case 0x1f00000:
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MISC_DPRINTF("Read system control %2.2x\n", ret);
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break;
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case 0xa000000:
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MISC_DPRINTF("Read power management %2.2x\n", ret);
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break;
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}
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return ret;
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}
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static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
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slavio_misc_mem_readb,
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slavio_misc_mem_readb,
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slavio_misc_mem_readb,
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};
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static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
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slavio_misc_mem_writeb,
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slavio_misc_mem_writeb,
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slavio_misc_mem_writeb,
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};
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static void slavio_misc_save(QEMUFile *f, void *opaque)
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{
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MiscState *s = opaque;
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qemu_put_be32s(f, &s->irq);
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qemu_put_8s(f, &s->config);
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qemu_put_8s(f, &s->aux1);
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qemu_put_8s(f, &s->aux2);
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qemu_put_8s(f, &s->diag);
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qemu_put_8s(f, &s->mctrl);
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}
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static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
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{
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MiscState *s = opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_be32s(f, &s->irq);
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qemu_get_8s(f, &s->config);
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qemu_get_8s(f, &s->aux1);
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qemu_get_8s(f, &s->aux2);
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qemu_get_8s(f, &s->diag);
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qemu_get_8s(f, &s->mctrl);
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return 0;
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}
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void *slavio_misc_init(uint32_t base, int irq)
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{
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int slavio_misc_io_memory;
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MiscState *s;
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s = qemu_mallocz(sizeof(MiscState));
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if (!s)
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return NULL;
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slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);
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// Slavio control
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cpu_register_physical_memory(base + 0x1800000, MISC_MAXADDR, slavio_misc_io_memory);
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// AUX 1
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cpu_register_physical_memory(base + 0x1900000, MISC_MAXADDR, slavio_misc_io_memory);
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// AUX 2
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cpu_register_physical_memory(base + 0x1910000, MISC_MAXADDR, slavio_misc_io_memory);
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// Diagnostics
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cpu_register_physical_memory(base + 0x1a00000, MISC_MAXADDR, slavio_misc_io_memory);
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// Modem control
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cpu_register_physical_memory(base + 0x1b00000, MISC_MAXADDR, slavio_misc_io_memory);
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// System control
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cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);
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// Power management
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cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory);
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s->irq = irq;
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register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s);
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qemu_register_reset(slavio_misc_reset, s);
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slavio_misc_reset(s);
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return s;
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}
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