708 lines
15 KiB
C
708 lines
15 KiB
C
#include "exec.h"
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//#define DEBUG_MMU
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void raise_exception(int tt)
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{
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env->exception_index = tt;
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cpu_loop_exit();
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}
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void do_fitos(void)
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{
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FT0 = (float) *((int32_t *)&FT1);
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}
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void do_fitod(void)
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{
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DT0 = (double) *((int32_t *)&FT1);
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}
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#endif
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void do_fabss(void)
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{
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FT0 = float32_abs(FT1);
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}
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#ifdef TARGET_SPARC64
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void do_fabsd(void)
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{
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DT0 = float64_abs(DT1);
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}
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#endif
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void do_fsqrts(void)
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{
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FT0 = float32_sqrt(FT1, &env->fp_status);
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}
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void do_fsqrtd(void)
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{
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DT0 = float64_sqrt(DT1, &env->fp_status);
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}
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#define FS 0
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void do_fcmps (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS;
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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void do_fcmpd (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS;
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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#ifdef TARGET_SPARC64
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#undef FS
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#define FS 22
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void do_fcmps_fcc1 (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS;
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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void do_fcmpd_fcc1 (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS;
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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#undef FS
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#define FS 24
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void do_fcmps_fcc2 (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS;
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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void do_fcmpd_fcc2 (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS;
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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#undef FS
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#define FS 26
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void do_fcmps_fcc3 (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (FT0 < FT1) {
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T0 = FSR_FCC0 << FS;
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} else if (FT0 > FT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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void do_fcmpd_fcc3 (void)
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS;
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0;
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raise_exception(TT_FP_EXCP);
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} else {
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env->fsr |= FSR_NVA;
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}
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} else if (DT0 < DT1) {
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T0 = FSR_FCC0 << FS;
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} else if (DT0 > DT1) {
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T0 = FSR_FCC1 << FS;
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} else {
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T0 = 0;
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}
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env->fsr |= T0;
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}
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#undef FS
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#endif
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#ifndef TARGET_SPARC64
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void helper_ld_asi(int asi, int size, int sign)
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{
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uint32_t ret;
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switch (asi) {
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case 3: /* MMU probe */
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{
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int mmulev;
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mmulev = (T0 >> 8) & 15;
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if (mmulev > 4)
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ret = 0;
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else {
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ret = mmu_probe(T0, mmulev);
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//bswap32s(&ret);
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}
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#ifdef DEBUG_MMU
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printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
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#endif
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}
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break;
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case 4: /* read MMU regs */
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{
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int reg = (T0 >> 8) & 0xf;
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ret = env->mmuregs[reg];
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if (reg == 3) /* Fault status cleared on read */
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env->mmuregs[reg] = 0;
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#ifdef DEBUG_MMU
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printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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#endif
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}
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break;
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case 0x20 ... 0x2f: /* MMU passthrough */
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cpu_physical_memory_read(T0, (void *) &ret, size);
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if (size == 4)
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tswap32s(&ret);
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else if (size == 2)
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tswap16s((uint16_t *)&ret);
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break;
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default:
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ret = 0;
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break;
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}
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T1 = ret;
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}
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void helper_st_asi(int asi, int size, int sign)
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{
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switch(asi) {
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case 3: /* MMU flush */
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{
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int mmulev;
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mmulev = (T0 >> 8) & 15;
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#ifdef DEBUG_MMU
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printf("mmu flush level %d\n", mmulev);
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#endif
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switch (mmulev) {
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case 0: // flush page
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tlb_flush_page(env, T0 & 0xfffff000);
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break;
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case 1: // flush segment (256k)
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case 2: // flush region (16M)
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case 3: // flush context (4G)
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case 4: // flush entire
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tlb_flush(env, 1);
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break;
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default:
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break;
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}
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#ifdef DEBUG_MMU
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dump_mmu();
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#endif
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return;
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}
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case 4: /* write MMU regs */
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{
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int reg = (T0 >> 8) & 0xf, oldreg;
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oldreg = env->mmuregs[reg];
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switch(reg) {
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case 0:
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env->mmuregs[reg] &= ~(MMU_E | MMU_NF);
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env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF);
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// Mappings generated during no-fault mode or MMU
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// disabled mode are invalid in normal mode
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if (oldreg != env->mmuregs[reg])
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tlb_flush(env, 1);
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break;
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case 2:
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env->mmuregs[reg] = T1;
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if (oldreg != env->mmuregs[reg]) {
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/* we flush when the MMU context changes because
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QEMU has no MMU context support */
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tlb_flush(env, 1);
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}
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break;
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case 3:
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case 4:
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break;
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default:
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env->mmuregs[reg] = T1;
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break;
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}
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#ifdef DEBUG_MMU
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if (oldreg != env->mmuregs[reg]) {
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printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
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}
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dump_mmu();
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#endif
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return;
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}
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case 0x17: /* Block copy, sta access */
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{
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// value (T1) = src
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// address (T0) = dst
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// copy 32 bytes
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int src = T1, dst = T0;
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uint8_t temp[32];
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tswap32s(&src);
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cpu_physical_memory_read(src, (void *) &temp, 32);
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cpu_physical_memory_write(dst, (void *) &temp, 32);
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}
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return;
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case 0x1f: /* Block fill, stda access */
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{
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// value (T1, T2)
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// address (T0) = dst
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// fill 32 bytes
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int i, dst = T0;
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uint64_t val;
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val = (((uint64_t)T1) << 32) | T2;
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tswap64s(&val);
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for (i = 0; i < 32; i += 8, dst += 8) {
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cpu_physical_memory_write(dst, (void *) &val, 8);
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}
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}
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return;
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case 0x20 ... 0x2f: /* MMU passthrough */
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{
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int temp = T1;
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if (size == 4)
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tswap32s(&temp);
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else if (size == 2)
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tswap16s((uint16_t *)&temp);
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cpu_physical_memory_write(T0, (void *) &temp, size);
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}
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return;
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default:
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return;
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}
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}
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#else
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void helper_ld_asi(int asi, int size, int sign)
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{
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uint64_t ret;
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if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
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raise_exception(TT_PRIV_INSN);
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switch (asi) {
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case 0x14: // Bypass
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case 0x15: // Bypass, non-cacheable
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{
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cpu_physical_memory_read(T0, (void *) &ret, size);
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if (size == 8)
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tswap64s(&ret);
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if (size == 4)
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tswap32s((uint32_t *)&ret);
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else if (size == 2)
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tswap16s((uint16_t *)&ret);
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break;
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}
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case 0x1c: // Bypass LE
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case 0x1d: // Bypass, non-cacheable LE
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// XXX
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break;
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case 0x45: // LSU
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ret = env->lsu;
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break;
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case 0x50: // I-MMU regs
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{
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int reg = (T0 >> 3) & 0xf;
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ret = env->immuregs[reg];
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break;
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}
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case 0x51: // I-MMU 8k TSB pointer
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case 0x52: // I-MMU 64k TSB pointer
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case 0x55: // I-MMU data access
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case 0x56: // I-MMU tag read
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break;
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case 0x58: // D-MMU regs
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{
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int reg = (T0 >> 3) & 0xf;
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ret = env->dmmuregs[reg];
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break;
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}
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case 0x59: // D-MMU 8k TSB pointer
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case 0x5a: // D-MMU 64k TSB pointer
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case 0x5b: // D-MMU data pointer
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case 0x5d: // D-MMU data access
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case 0x5e: // D-MMU tag read
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break;
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case 0x54: // I-MMU data in, WO
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case 0x57: // I-MMU demap, WO
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case 0x5c: // D-MMU data in, WO
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case 0x5f: // D-MMU demap, WO
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default:
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ret = 0;
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break;
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}
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T1 = ret;
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}
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void helper_st_asi(int asi, int size, int sign)
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{
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if (asi < 0x80 && (env->pstate & PS_PRIV) == 0)
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raise_exception(TT_PRIV_INSN);
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switch(asi) {
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case 0x14: // Bypass
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case 0x15: // Bypass, non-cacheable
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{
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target_ulong temp = T1;
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if (size == 8)
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tswap64s(&temp);
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else if (size == 4)
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tswap32s((uint32_t *)&temp);
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else if (size == 2)
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tswap16s((uint16_t *)&temp);
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cpu_physical_memory_write(T0, (void *) &temp, size);
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}
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return;
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case 0x1c: // Bypass LE
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case 0x1d: // Bypass, non-cacheable LE
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// XXX
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return;
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case 0x45: // LSU
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{
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uint64_t oldreg;
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oldreg = env->lsu;
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env->lsu = T1 & (DMMU_E | IMMU_E);
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// Mappings generated during D/I MMU disabled mode are
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// invalid in normal mode
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if (oldreg != env->lsu)
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tlb_flush(env, 1);
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return;
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}
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case 0x50: // I-MMU regs
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{
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int reg = (T0 >> 3) & 0xf;
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uint64_t oldreg;
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oldreg = env->immuregs[reg];
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switch(reg) {
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case 0: // RO
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case 4:
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return;
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case 1: // Not in I-MMU
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case 2:
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case 7:
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case 8:
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return;
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case 3: // SFSR
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if ((T1 & 1) == 0)
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T1 = 0; // Clear SFSR
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break;
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case 5: // TSB access
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case 6: // Tag access
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default:
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break;
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}
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env->immuregs[reg] = T1;
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#ifdef DEBUG_MMU
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if (oldreg != env->immuregs[reg]) {
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printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->immuregs[reg]);
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}
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dump_mmu();
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#endif
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return;
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}
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case 0x54: // I-MMU data in
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{
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unsigned int i;
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// Try finding an invalid entry
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for (i = 0; i < 64; i++) {
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
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env->itlb_tag[i] = env->immuregs[6];
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env->itlb_tte[i] = T1;
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return;
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}
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}
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// Try finding an unlocked entry
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for (i = 0; i < 64; i++) {
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if ((env->itlb_tte[i] & 0x40) == 0) {
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env->itlb_tag[i] = env->immuregs[6];
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env->itlb_tte[i] = T1;
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return;
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}
|
|
}
|
|
// error state?
|
|
return;
|
|
}
|
|
case 0x55: // I-MMU data access
|
|
{
|
|
unsigned int i = (T0 >> 3) & 0x3f;
|
|
|
|
env->itlb_tag[i] = env->immuregs[6];
|
|
env->itlb_tte[i] = T1;
|
|
return;
|
|
}
|
|
case 0x57: // I-MMU demap
|
|
return;
|
|
case 0x58: // D-MMU regs
|
|
{
|
|
int reg = (T0 >> 3) & 0xf;
|
|
uint64_t oldreg;
|
|
|
|
oldreg = env->dmmuregs[reg];
|
|
switch(reg) {
|
|
case 0: // RO
|
|
case 4:
|
|
return;
|
|
case 3: // SFSR
|
|
if ((T1 & 1) == 0) {
|
|
T1 = 0; // Clear SFSR, Fault address
|
|
env->dmmuregs[4] = 0;
|
|
}
|
|
env->dmmuregs[reg] = T1;
|
|
break;
|
|
case 1: // Primary context
|
|
case 2: // Secondary context
|
|
case 5: // TSB access
|
|
case 6: // Tag access
|
|
case 7: // Virtual Watchpoint
|
|
case 8: // Physical Watchpoint
|
|
default:
|
|
break;
|
|
}
|
|
env->dmmuregs[reg] = T1;
|
|
#ifdef DEBUG_MMU
|
|
if (oldreg != env->dmmuregs[reg]) {
|
|
printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->dmmuregs[reg]);
|
|
}
|
|
dump_mmu();
|
|
#endif
|
|
return;
|
|
}
|
|
case 0x5c: // D-MMU data in
|
|
{
|
|
unsigned int i;
|
|
|
|
// Try finding an invalid entry
|
|
for (i = 0; i < 64; i++) {
|
|
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
|
|
env->dtlb_tag[i] = env->dmmuregs[6];
|
|
env->dtlb_tte[i] = T1;
|
|
return;
|
|
}
|
|
}
|
|
// Try finding an unlocked entry
|
|
for (i = 0; i < 64; i++) {
|
|
if ((env->dtlb_tte[i] & 0x40) == 0) {
|
|
env->dtlb_tag[i] = env->dmmuregs[6];
|
|
env->dtlb_tte[i] = T1;
|
|
return;
|
|
}
|
|
}
|
|
// error state?
|
|
return;
|
|
}
|
|
case 0x5d: // D-MMU data access
|
|
{
|
|
unsigned int i = (T0 >> 3) & 0x3f;
|
|
|
|
env->dtlb_tag[i] = env->dmmuregs[6];
|
|
env->dtlb_tte[i] = T1;
|
|
return;
|
|
}
|
|
case 0x5f: // D-MMU demap
|
|
return;
|
|
case 0x51: // I-MMU 8k TSB pointer, RO
|
|
case 0x52: // I-MMU 64k TSB pointer, RO
|
|
case 0x56: // I-MMU tag read, RO
|
|
case 0x59: // D-MMU 8k TSB pointer, RO
|
|
case 0x5a: // D-MMU 64k TSB pointer, RO
|
|
case 0x5b: // D-MMU data pointer, RO
|
|
case 0x5e: // D-MMU tag read, RO
|
|
default:
|
|
return;
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifndef TARGET_SPARC64
|
|
void helper_rett()
|
|
{
|
|
unsigned int cwp;
|
|
|
|
env->psret = 1;
|
|
cwp = (env->cwp + 1) & (NWINDOWS - 1);
|
|
if (env->wim & (1 << cwp)) {
|
|
raise_exception(TT_WIN_UNF);
|
|
}
|
|
set_cwp(cwp);
|
|
env->psrs = env->psrps;
|
|
}
|
|
#endif
|
|
|
|
void helper_ldfsr(void)
|
|
{
|
|
int rnd_mode;
|
|
switch (env->fsr & FSR_RD_MASK) {
|
|
case FSR_RD_NEAREST:
|
|
rnd_mode = float_round_nearest_even;
|
|
break;
|
|
default:
|
|
case FSR_RD_ZERO:
|
|
rnd_mode = float_round_to_zero;
|
|
break;
|
|
case FSR_RD_POS:
|
|
rnd_mode = float_round_up;
|
|
break;
|
|
case FSR_RD_NEG:
|
|
rnd_mode = float_round_down;
|
|
break;
|
|
}
|
|
set_float_rounding_mode(rnd_mode, &env->fp_status);
|
|
}
|
|
|
|
void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f)
|
|
{
|
|
int exptemp;
|
|
|
|
*pmant = ldexp(frexp(f, &exptemp), 53);
|
|
*pexp = exptemp;
|
|
}
|
|
|
|
double cpu_put_fp64(uint64_t mant, uint16_t exp)
|
|
{
|
|
return ldexp((double) mant, exp - 53);
|
|
}
|
|
|
|
void helper_debug()
|
|
{
|
|
env->exception_index = EXCP_DEBUG;
|
|
cpu_loop_exit();
|
|
}
|
|
|
|
#ifndef TARGET_SPARC64
|
|
void do_wrpsr()
|
|
{
|
|
PUT_PSR(env, T0);
|
|
}
|
|
|
|
void do_rdpsr()
|
|
{
|
|
T0 = GET_PSR(env);
|
|
}
|
|
|
|
#else
|
|
|
|
void do_popc()
|
|
{
|
|
T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL);
|
|
T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL);
|
|
T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL);
|
|
T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL);
|
|
T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL);
|
|
T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL);
|
|
}
|
|
#endif
|