389 lines
10 KiB
C
389 lines
10 KiB
C
/*
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* IMX31 UARTS
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*
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* Copyright (c) 2008 OKL
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* Originally Written by Hans Jiang
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* Copyright (c) 2011 NICTA Pty Ltd.
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* This is a `bare-bones' implementation of the IMX series serial ports.
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* TODO:
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* -- implement FIFOs. The real hardware has 32 word transmit
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* and receive FIFOs; we currently use a 1-char buffer
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* -- implement DMA
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* -- implement BAUD-rate and modem lines, for when the backend
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* is a real serial device.
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*/
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#include "qemu/osdep.h"
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#include "hw/char/imx_serial.h"
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#ifndef DEBUG_IMX_UART
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#define DEBUG_IMX_UART 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_UART) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
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__func__, ##args); \
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} \
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} while (0)
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static const VMStateDescription vmstate_imx_serial = {
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.name = TYPE_IMX_SERIAL,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(readbuff, IMXSerialState),
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VMSTATE_UINT32(usr1, IMXSerialState),
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VMSTATE_UINT32(usr2, IMXSerialState),
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VMSTATE_UINT32(ucr1, IMXSerialState),
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VMSTATE_UINT32(uts1, IMXSerialState),
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VMSTATE_UINT32(onems, IMXSerialState),
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VMSTATE_UINT32(ufcr, IMXSerialState),
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VMSTATE_UINT32(ubmr, IMXSerialState),
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VMSTATE_UINT32(ubrc, IMXSerialState),
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VMSTATE_UINT32(ucr3, IMXSerialState),
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VMSTATE_UINT32(ucr4, IMXSerialState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx_update(IMXSerialState *s)
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{
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uint32_t usr1;
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uint32_t usr2;
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uint32_t mask;
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/*
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* Lucky for us TRDY and RRDY has the same offset in both USR1 and
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* UCR1, so we can get away with something as simple as the
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* following:
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*/
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usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
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/*
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* Bits that we want in USR2 are not as conveniently laid out,
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* unfortunately.
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*/
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mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
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/*
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* TCEN and TXDC are both bit 3
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* RDR and DREN are both bit 0
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*/
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mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
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usr2 = s->usr2 & mask;
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qemu_set_irq(s->irq, usr1 || usr2);
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}
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static void imx_serial_reset(IMXSerialState *s)
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{
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s->usr1 = USR1_TRDY | USR1_RXDS;
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/*
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* Fake attachment of a terminal: assert RTS.
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*/
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s->usr1 |= USR1_RTSS;
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s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
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s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
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s->ucr1 = 0;
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s->ucr2 = UCR2_SRST;
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s->ucr3 = 0x700;
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s->ubmr = 0;
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s->ubrc = 4;
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s->readbuff = URXD_ERR;
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}
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static void imx_serial_reset_at_boot(DeviceState *dev)
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{
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IMXSerialState *s = IMX_SERIAL(dev);
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imx_serial_reset(s);
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/*
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* enable the uart on boot, so messages from the linux decompresser
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* are visible. On real hardware this is done by the boot rom
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* before anything else is loaded.
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*/
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s->ucr1 = UCR1_UARTEN;
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s->ucr2 = UCR2_TXEN;
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}
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static uint64_t imx_serial_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXSerialState *s = (IMXSerialState *)opaque;
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uint32_t c;
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DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
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switch (offset >> 2) {
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case 0x0: /* URXD */
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c = s->readbuff;
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if (!(s->uts1 & UTS1_RXEMPTY)) {
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/* Character is valid */
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c |= URXD_CHARRDY;
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s->usr1 &= ~USR1_RRDY;
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s->usr2 &= ~USR2_RDR;
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s->uts1 |= UTS1_RXEMPTY;
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imx_update(s);
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qemu_chr_fe_accept_input(&s->chr);
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}
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return c;
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case 0x20: /* UCR1 */
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return s->ucr1;
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case 0x21: /* UCR2 */
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return s->ucr2;
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case 0x25: /* USR1 */
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return s->usr1;
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case 0x26: /* USR2 */
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return s->usr2;
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case 0x2A: /* BRM Modulator */
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return s->ubmr;
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case 0x2B: /* Baud Rate Count */
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return s->ubrc;
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case 0x2d: /* Test register */
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return s->uts1;
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case 0x24: /* UFCR */
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return s->ufcr;
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case 0x2c:
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return s->onems;
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case 0x22: /* UCR3 */
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return s->ucr3;
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case 0x23: /* UCR4 */
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return s->ucr4;
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case 0x29: /* BRM Incremental */
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return 0x0; /* TODO */
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
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return 0;
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}
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}
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static void imx_serial_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IMXSerialState *s = (IMXSerialState *)opaque;
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Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
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unsigned char ch;
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DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
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offset, (unsigned int)value, chr ? chr->label : "NODEV");
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switch (offset >> 2) {
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case 0x10: /* UTXD */
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ch = value;
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if (s->ucr2 & UCR2_TXEN) {
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/* XXX this blocks entire thread. Rewrite to use
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* qemu_chr_fe_write and background I/O callbacks */
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qemu_chr_fe_write_all(&s->chr, &ch, 1);
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s->usr1 &= ~USR1_TRDY;
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s->usr2 &= ~USR2_TXDC;
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imx_update(s);
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s->usr1 |= USR1_TRDY;
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s->usr2 |= USR2_TXDC;
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imx_update(s);
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}
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break;
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case 0x20: /* UCR1 */
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s->ucr1 = value & 0xffff;
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DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
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imx_update(s);
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break;
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case 0x21: /* UCR2 */
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/*
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* Only a few bits in control register 2 are implemented as yet.
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* If it's intended to use a real serial device as a back-end, this
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* register will have to be implemented more fully.
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*/
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if (!(value & UCR2_SRST)) {
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imx_serial_reset(s);
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imx_update(s);
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value |= UCR2_SRST;
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}
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if (value & UCR2_RXEN) {
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if (!(s->ucr2 & UCR2_RXEN)) {
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qemu_chr_fe_accept_input(&s->chr);
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}
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}
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s->ucr2 = value & 0xffff;
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break;
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case 0x25: /* USR1 */
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value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
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USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
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s->usr1 &= ~value;
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break;
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case 0x26: /* USR2 */
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/*
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* Writing 1 to some bits clears them; all other
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* values are ignored
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*/
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value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
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USR2_RIDELT | USR2_IRINT | USR2_WAKE |
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USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
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s->usr2 &= ~value;
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break;
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/*
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* Linux expects to see what it writes to these registers
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* We don't currently alter the baud rate
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*/
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case 0x29: /* UBIR */
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s->ubrc = value & 0xffff;
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break;
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case 0x2a: /* UBMR */
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s->ubmr = value & 0xffff;
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break;
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case 0x2c: /* One ms reg */
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s->onems = value & 0xffff;
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break;
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case 0x24: /* FIFO control register */
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s->ufcr = value & 0xffff;
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break;
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case 0x22: /* UCR3 */
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s->ucr3 = value & 0xffff;
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break;
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case 0x23: /* UCR4 */
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s->ucr4 = value & 0xffff;
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imx_update(s);
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break;
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case 0x2d: /* UTS1 */
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qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
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/* TODO */
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
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}
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}
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static int imx_can_receive(void *opaque)
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{
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IMXSerialState *s = (IMXSerialState *)opaque;
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return !(s->usr1 & USR1_RRDY);
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}
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static void imx_put_data(void *opaque, uint32_t value)
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{
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IMXSerialState *s = (IMXSerialState *)opaque;
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DPRINTF("received char\n");
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s->usr1 |= USR1_RRDY;
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s->usr2 |= USR2_RDR;
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s->uts1 &= ~UTS1_RXEMPTY;
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s->readbuff = value;
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if (value & URXD_BRK) {
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s->usr2 |= USR2_BRCD;
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}
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imx_update(s);
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}
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static void imx_receive(void *opaque, const uint8_t *buf, int size)
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{
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imx_put_data(opaque, *buf);
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}
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static void imx_event(void *opaque, int event)
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{
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if (event == CHR_EVENT_BREAK) {
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imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR);
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}
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}
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static const struct MemoryRegionOps imx_serial_ops = {
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.read = imx_serial_read,
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.write = imx_serial_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void imx_serial_realize(DeviceState *dev, Error **errp)
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{
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IMXSerialState *s = IMX_SERIAL(dev);
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DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
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qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
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imx_event, NULL, s, NULL, true);
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}
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static void imx_serial_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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IMXSerialState *s = IMX_SERIAL(obj);
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memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
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TYPE_IMX_SERIAL, 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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}
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static Property imx_serial_properties[] = {
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DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void imx_serial_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx_serial_realize;
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dc->vmsd = &vmstate_imx_serial;
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dc->reset = imx_serial_reset_at_boot;
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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dc->desc = "i.MX series UART";
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dc->props = imx_serial_properties;
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}
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static const TypeInfo imx_serial_info = {
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.name = TYPE_IMX_SERIAL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXSerialState),
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.instance_init = imx_serial_init,
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.class_init = imx_serial_class_init,
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};
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static void imx_serial_register_types(void)
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{
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type_register_static(&imx_serial_info);
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}
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type_init(imx_serial_register_types)
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