Peter Maydell 34f9052967 target-arm: Convert cp15 crn=9 registers ... Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2012-06-20 12:08:16 +00:00
..
arm-semi.c	build: move obj-TARGET-y variables to nested Makefile.objs	2012-06-07 07:17:36 +02:00
cpu-qom.h	target-arm: Add register_cp_regs_for_features()	2012-06-20 12:02:54 +00:00
cpu.c	target-arm: Convert cp15 crn=9 registers	2012-06-20 12:08:16 +00:00
cpu.h	target-arm: convert cp15 crn=7 registers	2012-06-20 12:07:11 +00:00
helper.c	target-arm: Convert cp15 crn=9 registers	2012-06-20 12:08:16 +00:00
helper.h	target-arm: Convert TEECR, TEEHBR to new scheme	2012-06-20 12:04:08 +00:00
iwmmxt_helper.c
machine.c
Makefile.objs	build: move other target-*/ objects to nested Makefile.objs	2012-06-07 09:21:11 +02:00
neon_helper.c	target-arm: When setting FPSCR.QC, don't clear other FPSCR bits	2012-05-10 12:56:08 +00:00
op_addsub.h
op_helper.c	target-arm: initial coprocessor register framework	2012-06-20 12:01:02 +00:00
translate.c	target-arm: Convert performance monitor registers	2012-06-20 12:05:17 +00:00