c2da8a8b90
The uboot in the previous release of the SDK was using a hardcoded value for memory size. This is not true anymore, the value is now retrieved from the memory controller. Below is a model for this device, only supporting unlock and configuration. Without it, we endup running a guest with 64MB, which is a bit low nowdays. It uses a 'silicon-rev' property and ram_size to build a default value. Some bits should be linked to SCU strapping registers but it seems a bit complex to add for the current need. The model is ready for the AST2500 SOC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
45 lines
974 B
C
45 lines
974 B
C
/*
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* ASPEED AST2400 SoC
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef AST2400_H
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#define AST2400_H
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#include "hw/arm/arm.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/ssi/aspeed_smc.h"
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typedef struct AST2400State {
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/*< private >*/
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DeviceState parent;
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/*< public >*/
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ARMCPU *cpu;
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MemoryRegion iomem;
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AspeedVICState vic;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedSCUState scu;
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AspeedSMCState smc;
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AspeedSMCState spi;
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AspeedSDMCState sdmc;
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} AST2400State;
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#define TYPE_AST2400 "ast2400"
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#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400)
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#define AST2400_SDRAM_BASE 0x40000000
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#endif /* AST2400_H */
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