647 lines
21 KiB
C
647 lines
21 KiB
C
/*
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* ARM Generic Interrupt Controller v3
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*
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* Copyright (c) 2016 Linaro Limited
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* Written by Peter Maydell
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*
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* This code is licensed under the GPL, version 2 or (at your option)
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* any later version.
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*/
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/* This file contains the code for the system register interface
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* portions of the GICv3.
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*/
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#include "qemu/osdep.h"
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#include "trace.h"
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#include "gicv3_internal.h"
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#include "cpu.h"
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static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
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{
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/* Given the CPU, find the right GICv3CPUState struct.
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* Since we registered the CPU interface with the EL change hook as
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* the opaque pointer, we can just directly get from the CPU to it.
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*/
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return arm_get_el_change_hook_opaque(arm_env_get_cpu(env));
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}
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static bool gicv3_use_ns_bank(CPUARMState *env)
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{
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/* Return true if we should use the NonSecure bank for a banked GIC
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* CPU interface register. Note that this differs from the
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* access_secure_reg() function because GICv3 banked registers are
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* banked even for AArch64, unlike the other CPU system registers.
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*/
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return !arm_is_secure_below_el3(env);
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}
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static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint32_t value = cs->icc_pmr_el1;
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if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
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(env->cp15.scr_el3 & SCR_FIQ)) {
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/* NS access and Group 0 is inaccessible to NS: return the
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* NS view of the current priority
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*/
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if (value & 0x80) {
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/* Secure priorities not visible to NS */
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value = 0;
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} else if (value != 0xff) {
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value = (value << 1) & 0xff;
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}
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}
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trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
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value &= 0xff;
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if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
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(env->cp15.scr_el3 & SCR_FIQ)) {
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/* NS access and Group 0 is inaccessible to NS: return the
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* NS view of the current priority
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*/
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if (!(cs->icc_pmr_el1 & 0x80)) {
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/* Current PMR in the secure range, don't allow NS to change it */
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return;
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}
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value = (value >> 1) & 0x80;
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}
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cs->icc_pmr_el1 = value;
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gicv3_cpuif_update(cs);
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}
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static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
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bool satinc = false;
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uint64_t bpr;
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) &&
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(cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) {
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/* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses
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* modify BPR0
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*/
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grp = GICV3_G0;
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}
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if (grp == GICV3_G1NS && arm_current_el(env) < 3 &&
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(cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
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/* reads return bpr0 + 1 sat to 7, writes ignored */
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grp = GICV3_G0;
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satinc = true;
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}
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bpr = cs->icc_bpr[grp];
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if (satinc) {
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bpr++;
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bpr = MIN(bpr, 7);
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}
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trace_gicv3_icc_bpr_read(gicv3_redist_affid(cs), bpr);
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return bpr;
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}
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static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
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trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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if (grp == GICV3_G1 && !arm_is_el3_or_mon(env) &&
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(cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) {
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/* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses
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* modify BPR0
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*/
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grp = GICV3_G0;
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}
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if (grp == GICV3_G1NS && arm_current_el(env) < 3 &&
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(cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
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/* reads return bpr0 + 1 sat to 7, writes ignored */
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return;
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}
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cs->icc_bpr[grp] = value & 7;
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gicv3_cpuif_update(cs);
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}
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static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t value;
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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value = cs->icc_apr[grp][regno];
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trace_gicv3_icc_ap_read(regno, gicv3_redist_affid(cs), value);
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return value;
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}
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static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
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trace_gicv3_icc_ap_write(regno, gicv3_redist_affid(cs), value);
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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/* It's not possible to claim that a Non-secure interrupt is active
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* at a priority outside the Non-secure range (128..255), since this
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* would otherwise allow malicious NS code to block delivery of S interrupts
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* by writing a bad value to these registers.
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*/
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if (grp == GICV3_G1NS && regno < 2 && arm_feature(env, ARM_FEATURE_EL3)) {
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return;
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}
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cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU;
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gicv3_cpuif_update(cs);
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}
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static uint64_t icc_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0;
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uint64_t value;
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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value = cs->icc_igrpen[grp];
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trace_gicv3_icc_igrpen_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0;
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trace_gicv3_icc_igrpen_write(gicv3_redist_affid(cs), value);
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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cs->icc_igrpen[grp] = value & ICC_IGRPEN_ENABLE;
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gicv3_cpuif_update(cs);
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}
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static uint64_t icc_igrpen1_el3_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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/* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */
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return cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1);
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}
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static void icc_igrpen1_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs), value);
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/* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */
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cs->icc_igrpen[GICV3_G1NS] = extract32(value, 0, 1);
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cs->icc_igrpen[GICV3_G1] = extract32(value, 1, 1);
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gicv3_cpuif_update(cs);
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}
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static uint64_t icc_ctlr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S;
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uint64_t value;
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value = cs->icc_ctlr_el1[bank];
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trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static void icc_ctlr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S;
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uint64_t mask;
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trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs), value);
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/* Only CBPR and EOIMODE can be RW;
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* for us PMHE is RAZ/WI (we don't implement 1-of-N interrupts or
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* the asseciated priority-based routing of them);
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* if EL3 is implemented and GICD_CTLR.DS == 0, then PMHE and CBPR are RO.
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*/
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if (arm_feature(env, ARM_FEATURE_EL3) &&
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((cs->gic->gicd_ctlr & GICD_CTLR_DS) == 0)) {
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mask = ICC_CTLR_EL1_EOIMODE;
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} else {
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mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE;
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}
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cs->icc_ctlr_el1[bank] &= ~mask;
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cs->icc_ctlr_el1[bank] |= (value & mask);
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gicv3_cpuif_update(cs);
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}
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static uint64_t icc_ctlr_el3_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t value;
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value = cs->icc_ctlr_el3;
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if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) {
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value |= ICC_CTLR_EL3_EOIMODE_EL1NS;
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}
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if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) {
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value |= ICC_CTLR_EL3_CBPR_EL1NS;
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}
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if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) {
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value |= ICC_CTLR_EL3_EOIMODE_EL1S;
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}
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if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) {
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value |= ICC_CTLR_EL3_CBPR_EL1S;
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}
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trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t mask;
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trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
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/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
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cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
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if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
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cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
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}
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if (value & ICC_CTLR_EL3_CBPR_EL1NS) {
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cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
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}
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cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
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if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
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cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
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}
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if (value & ICC_CTLR_EL3_CBPR_EL1S) {
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cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR;
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}
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/* The only bit stored in icc_ctlr_el3 which is writeable is EOIMODE_EL3: */
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mask = ICC_CTLR_EL3_EOIMODE_EL3;
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cs->icc_ctlr_el3 &= ~mask;
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cs->icc_ctlr_el3 |= (value & mask);
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gicv3_cpuif_update(cs);
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}
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static CPAccessResult gicv3_irqfiq_access(CPUARMState *env,
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const ARMCPRegInfo *ri, bool isread)
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{
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CPAccessResult r = CP_ACCESS_OK;
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if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) {
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switch (arm_current_el(env)) {
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case 1:
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if (arm_is_secure_below_el3(env) ||
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((env->cp15.hcr_el2 & (HCR_IMO | HCR_FMO)) == 0)) {
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r = CP_ACCESS_TRAP_EL3;
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}
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break;
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case 2:
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r = CP_ACCESS_TRAP_EL3;
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break;
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case 3:
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if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
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r = CP_ACCESS_TRAP_EL3;
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}
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default:
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g_assert_not_reached();
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}
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}
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if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
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r = CP_ACCESS_TRAP;
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}
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return r;
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}
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static CPAccessResult gicv3_fiq_access(CPUARMState *env,
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const ARMCPRegInfo *ri, bool isread)
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{
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CPAccessResult r = CP_ACCESS_OK;
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if (env->cp15.scr_el3 & SCR_FIQ) {
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switch (arm_current_el(env)) {
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case 1:
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if (arm_is_secure_below_el3(env) ||
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((env->cp15.hcr_el2 & HCR_FMO) == 0)) {
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r = CP_ACCESS_TRAP_EL3;
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}
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break;
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case 2:
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r = CP_ACCESS_TRAP_EL3;
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break;
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case 3:
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if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
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r = CP_ACCESS_TRAP_EL3;
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}
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default:
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g_assert_not_reached();
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}
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}
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if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
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r = CP_ACCESS_TRAP;
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}
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return r;
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}
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static CPAccessResult gicv3_irq_access(CPUARMState *env,
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const ARMCPRegInfo *ri, bool isread)
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{
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CPAccessResult r = CP_ACCESS_OK;
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if (env->cp15.scr_el3 & SCR_IRQ) {
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switch (arm_current_el(env)) {
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case 1:
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if (arm_is_secure_below_el3(env) ||
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((env->cp15.hcr_el2 & HCR_IMO) == 0)) {
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r = CP_ACCESS_TRAP_EL3;
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}
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break;
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case 2:
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r = CP_ACCESS_TRAP_EL3;
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break;
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case 3:
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if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
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r = CP_ACCESS_TRAP_EL3;
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
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r = CP_ACCESS_TRAP;
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}
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return r;
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}
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static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V |
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(1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
|
|
(7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
|
|
cs->icc_ctlr_el1[GICV3_NS] = ICC_CTLR_EL1_A3V |
|
|
(1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
|
|
(7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
|
|
cs->icc_pmr_el1 = 0;
|
|
cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
|
|
cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
|
|
if (arm_feature(env, ARM_FEATURE_EL3)) {
|
|
cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
|
|
} else {
|
|
cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
|
|
}
|
|
memset(cs->icc_apr, 0, sizeof(cs->icc_apr));
|
|
memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen));
|
|
cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V |
|
|
(1 << ICC_CTLR_EL3_IDBITS_SHIFT) |
|
|
(7 << ICC_CTLR_EL3_PRIBITS_SHIFT);
|
|
}
|
|
|
|
static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
|
|
{ .name = "ICC_PMR_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irqfiq_access,
|
|
.readfn = icc_pmr_read,
|
|
.writefn = icc_pmr_write,
|
|
/* We hang the whole cpu interface reset routine off here
|
|
* rather than parcelling it out into one little function
|
|
* per register
|
|
*/
|
|
.resetfn = icc_reset,
|
|
},
|
|
{ .name = "ICC_BPR0_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_fiq_access,
|
|
.fieldoffset = offsetof(GICv3CPUState, icc_bpr[GICV3_G0]),
|
|
.writefn = icc_bpr_write,
|
|
},
|
|
{ .name = "ICC_AP0R0_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_fiq_access,
|
|
.fieldoffset = offsetof(GICv3CPUState, icc_apr[GICV3_G0][0]),
|
|
.writefn = icc_ap_write,
|
|
},
|
|
{ .name = "ICC_AP0R1_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 5,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_fiq_access,
|
|
.fieldoffset = offsetof(GICv3CPUState, icc_apr[GICV3_G0][1]),
|
|
.writefn = icc_ap_write,
|
|
},
|
|
{ .name = "ICC_AP0R2_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 6,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_fiq_access,
|
|
.fieldoffset = offsetof(GICv3CPUState, icc_apr[GICV3_G0][2]),
|
|
.writefn = icc_ap_write,
|
|
},
|
|
{ .name = "ICC_AP0R3_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 7,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_fiq_access,
|
|
.fieldoffset = offsetof(GICv3CPUState, icc_apr[GICV3_G0][3]),
|
|
.writefn = icc_ap_write,
|
|
},
|
|
/* All the ICC_AP1R*_EL1 registers are banked */
|
|
{ .name = "ICC_AP1R0_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irq_access,
|
|
.readfn = icc_ap_read,
|
|
.writefn = icc_ap_write,
|
|
},
|
|
{ .name = "ICC_AP1R1_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irq_access,
|
|
.readfn = icc_ap_read,
|
|
.writefn = icc_ap_write,
|
|
},
|
|
{ .name = "ICC_AP1R2_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 2,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irq_access,
|
|
.readfn = icc_ap_read,
|
|
.writefn = icc_ap_write,
|
|
},
|
|
{ .name = "ICC_AP1R3_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 3,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irq_access,
|
|
.readfn = icc_ap_read,
|
|
.writefn = icc_ap_write,
|
|
},
|
|
/* This register is banked */
|
|
{ .name = "ICC_BPR1_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 3,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irq_access,
|
|
.readfn = icc_bpr_read,
|
|
.writefn = icc_bpr_write,
|
|
},
|
|
/* This register is banked */
|
|
{ .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irqfiq_access,
|
|
.readfn = icc_ctlr_el1_read,
|
|
.writefn = icc_ctlr_el1_write,
|
|
},
|
|
{ .name = "ICC_SRE_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5,
|
|
.type = ARM_CP_NO_RAW | ARM_CP_CONST,
|
|
.access = PL1_RW,
|
|
/* We don't support IRQ/FIQ bypass and system registers are
|
|
* always enabled, so all our bits are RAZ/WI or RAO/WI.
|
|
* This register is banked but since it's constant we don't
|
|
* need to do anything special.
|
|
*/
|
|
.resetvalue = 0x7,
|
|
},
|
|
{ .name = "ICC_IGRPEN0_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_fiq_access,
|
|
.fieldoffset = offsetof(GICv3CPUState, icc_igrpen[GICV3_G0]),
|
|
.writefn = icc_igrpen_write,
|
|
},
|
|
/* This register is banked */
|
|
{ .name = "ICC_IGRPEN1_EL1", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL1_RW, .accessfn = gicv3_irq_access,
|
|
.readfn = icc_igrpen_read,
|
|
.writefn = icc_igrpen_write,
|
|
},
|
|
{ .name = "ICC_SRE_EL2", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 5,
|
|
.type = ARM_CP_NO_RAW | ARM_CP_CONST,
|
|
.access = PL2_RW,
|
|
/* We don't support IRQ/FIQ bypass and system registers are
|
|
* always enabled, so all our bits are RAZ/WI or RAO/WI.
|
|
*/
|
|
.resetvalue = 0xf,
|
|
},
|
|
{ .name = "ICC_CTLR_EL3", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 4,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL3_RW,
|
|
.fieldoffset = offsetof(GICv3CPUState, icc_ctlr_el3),
|
|
.readfn = icc_ctlr_el3_read,
|
|
.writefn = icc_ctlr_el3_write,
|
|
},
|
|
{ .name = "ICC_SRE_EL3", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 5,
|
|
.type = ARM_CP_NO_RAW | ARM_CP_CONST,
|
|
.access = PL3_RW,
|
|
/* We don't support IRQ/FIQ bypass and system registers are
|
|
* always enabled, so all our bits are RAZ/WI or RAO/WI.
|
|
*/
|
|
.resetvalue = 0xf,
|
|
},
|
|
{ .name = "ICC_IGRPEN1_EL3", .state = ARM_CP_STATE_BOTH,
|
|
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 12, .opc2 = 7,
|
|
.type = ARM_CP_IO | ARM_CP_NO_RAW,
|
|
.access = PL3_RW,
|
|
.readfn = icc_igrpen1_el3_read,
|
|
.writefn = icc_igrpen1_el3_write,
|
|
},
|
|
REGINFO_SENTINEL
|
|
};
|
|
|
|
static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
|
|
{
|
|
/* Do nothing for now. */
|
|
}
|
|
|
|
void gicv3_init_cpuif(GICv3State *s)
|
|
{
|
|
/* Called from the GICv3 realize function; register our system
|
|
* registers with the CPU
|
|
*/
|
|
int i;
|
|
|
|
for (i = 0; i < s->num_cpu; i++) {
|
|
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
|
|
GICv3CPUState *cs = &s->cpu[i];
|
|
|
|
/* Note that we can't just use the GICv3CPUState as an opaque pointer
|
|
* in define_arm_cp_regs_with_opaque(), because when we're called back
|
|
* it might be with code translated by CPU 0 but run by CPU 1, in
|
|
* which case we'd get the wrong value.
|
|
* So instead we define the regs with no ri->opaque info, and
|
|
* get back to the GICv3CPUState from the ARMCPU by reading back
|
|
* the opaque pointer from the el_change_hook, which we're going
|
|
* to need to register anyway.
|
|
*/
|
|
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
|
|
arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
|
|
}
|
|
}
|