361c33f6b8
Implement the machinery for fine-grained traps on normal sysregs. Any sysreg with a fine-grained trap will set the new field to indicate which FGT register bit it should trap on. FGT traps only happen when an AArch64 EL2 enables them for an AArch64 EL1. They therefore are only relevant for AArch32 cpregs when the cpreg can be accessed from EL0. The logic in access_check_cp_reg() will check this, so it is safe to add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo. The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname which can be used to specify the FGT bit, eg .fgt = FGT_AFSR0_EL1 (We assume that there is no bit name duplication across the FGT registers, for brevity's sake.) Subsequent commits will add the .fgt fields to the relevant register definitions and define the FGT_nnn values for them. Note that some of the FGT traps are for instructions that we don't handle via the cpregs mechanisms (mostly these are instruction traps). Those we will have to handle separately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
641 lines
22 KiB
C
641 lines
22 KiB
C
#ifndef TARGET_ARM_TRANSLATE_H
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#define TARGET_ARM_TRANSLATE_H
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#include "exec/translator.h"
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#include "internals.h"
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/* internal defines */
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/*
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* Save pc_save across a branch, so that we may restore the value from
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* before the branch at the point the label is emitted.
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*/
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typedef struct DisasLabel {
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TCGLabel *label;
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target_ulong pc_save;
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} DisasLabel;
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typedef struct DisasContext {
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DisasContextBase base;
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const ARMISARegisters *isar;
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/* The address of the current instruction being translated. */
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target_ulong pc_curr;
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/*
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* For TARGET_TB_PCREL, the full value of cpu_pc is not known
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* (although the page offset is known). For convenience, the
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* translation loop uses the full virtual address that triggered
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* the translation, from base.pc_start through pc_curr.
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* For efficiency, we do not update cpu_pc for every instruction.
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* Instead, pc_save has the value of pc_curr at the time of the
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* last update to cpu_pc, which allows us to compute the addend
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* needed to bring cpu_pc current: pc_curr - pc_save.
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* If cpu_pc now contains the destination of an indirect branch,
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* pc_save contains -1 to indicate that relative updates are no
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* longer possible.
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*/
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target_ulong pc_save;
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target_ulong page_start;
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uint32_t insn;
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/* Nonzero if this instruction has been conditionally skipped. */
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int condjmp;
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/* The label that will be jumped to when the instruction is skipped. */
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DisasLabel condlabel;
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/* Thumb-2 conditional execution bits. */
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int condexec_mask;
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int condexec_cond;
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/* M-profile ECI/ICI exception-continuable instruction state */
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int eci;
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/*
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* trans_ functions for insns which are continuable should set this true
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* after decode (ie after any UNDEF checks)
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*/
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bool eci_handled;
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int sctlr_b;
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MemOp be_data;
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#if !defined(CONFIG_USER_ONLY)
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int user;
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#endif
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ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
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uint8_t tbii; /* TBI1|TBI0 for insns */
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uint8_t tbid; /* TBI1|TBI0 for data */
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uint8_t tcma; /* TCMA1|TCMA0 for MTE */
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bool ns; /* Use non-secure CPREG bank on access */
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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int sve_excp_el; /* SVE exception EL or 0 if enabled */
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int sme_excp_el; /* SME exception EL or 0 if enabled */
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int vl; /* current vector length in bytes */
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int svl; /* current streaming vector length in bytes */
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bool vfp_enabled; /* FP enabled via FPSCR.EN */
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int vec_len;
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int vec_stride;
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bool v7m_handler_mode;
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bool v8m_secure; /* true if v8M and we're in Secure mode */
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bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
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bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
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bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
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bool v7m_lspact; /* FPCCR.LSPACT set */
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/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
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* so that top level loop can generate correct syndrome information.
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*/
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uint32_t svc_imm;
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int current_el;
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GHashTable *cp_regs;
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uint64_t features; /* CPU features bits */
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bool aarch64;
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bool thumb;
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/* Because unallocated encodings generate different exception syndrome
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* information from traps due to FP being disabled, we can't do a single
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* "is fp access disabled" check at a high level in the decode tree.
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* To help in catching bugs where the access check was forgotten in some
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* code path, we set this flag when the access check is done, and assert
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* that it is set at the point where we actually touch the FP regs.
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*/
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bool fp_access_checked;
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bool sve_access_checked;
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/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
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* single-step support).
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*/
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bool ss_active;
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bool pstate_ss;
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/* True if the insn just emitted was a load-exclusive instruction
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* (necessary for syndrome information for single step exceptions),
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* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
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*/
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bool is_ldex;
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/* True if AccType_UNPRIV should be used for LDTR et al */
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bool unpriv;
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/* True if v8.3-PAuth is active. */
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bool pauth_active;
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/* True if v8.5-MTE access to tags is enabled. */
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bool ata;
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/* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */
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bool mte_active[2];
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/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
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bool bt;
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/* True if any CP15 access is trapped by HSTR_EL2 */
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bool hstr_active;
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/* True if memory operations require alignment */
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bool align_mem;
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/* True if PSTATE.IL is set */
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bool pstate_il;
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/* True if PSTATE.SM is set. */
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bool pstate_sm;
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/* True if PSTATE.ZA is set. */
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bool pstate_za;
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/* True if non-streaming insns should raise an SME Streaming exception. */
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bool sme_trap_nonstreaming;
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/* True if the current instruction is non-streaming. */
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bool is_nonstreaming;
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/* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
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bool mve_no_pred;
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/* True if fine-grained traps are active */
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bool fgt_active;
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/*
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* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
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* < 0, set by the current instruction.
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*/
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int8_t btype;
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/* A copy of cpu->dcz_blocksize. */
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uint8_t dcz_blocksize;
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/* True if this page is guarded. */
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bool guarded_page;
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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/* TCG op of the current insn_start. */
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TCGOp *insn_start;
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#define TMP_A64_MAX 16
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int tmp_a64_count;
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TCGv_i64 tmp_a64[TMP_A64_MAX];
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} DisasContext;
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typedef struct DisasCompare {
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TCGCond cond;
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TCGv_i32 value;
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bool value_global;
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} DisasCompare;
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/* Share the TCG temporaries common between 32 and 64 bit modes. */
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extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
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extern TCGv_i64 cpu_exclusive_addr;
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extern TCGv_i64 cpu_exclusive_val;
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/*
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* Constant expanders for the decoders.
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*/
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static inline int negate(DisasContext *s, int x)
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{
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return -x;
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}
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static inline int plus_1(DisasContext *s, int x)
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{
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return x + 1;
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}
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static inline int plus_2(DisasContext *s, int x)
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{
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return x + 2;
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}
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static inline int plus_12(DisasContext *s, int x)
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{
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return x + 12;
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}
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static inline int times_2(DisasContext *s, int x)
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{
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return x * 2;
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}
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static inline int times_4(DisasContext *s, int x)
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{
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return x * 4;
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}
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static inline int times_2_plus_1(DisasContext *s, int x)
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{
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return x * 2 + 1;
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}
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static inline int rsub_64(DisasContext *s, int x)
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{
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return 64 - x;
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}
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static inline int rsub_32(DisasContext *s, int x)
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{
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return 32 - x;
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}
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static inline int rsub_16(DisasContext *s, int x)
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{
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return 16 - x;
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}
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static inline int rsub_8(DisasContext *s, int x)
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{
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return 8 - x;
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}
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static inline int neon_3same_fp_size(DisasContext *s, int x)
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{
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/* Convert 0==fp32, 1==fp16 into a MO_* value */
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return MO_32 - x;
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}
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static inline int arm_dc_feature(DisasContext *dc, int feature)
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{
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return (dc->features & (1ULL << feature)) != 0;
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}
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static inline int get_mem_index(DisasContext *s)
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{
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return arm_to_core_mmu_idx(s->mmu_idx);
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}
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static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
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{
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/* We don't need to save all of the syndrome so we mask and shift
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* out unneeded bits to help the sleb128 encoder do a better job.
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*/
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syn &= ARM_INSN_START_WORD2_MASK;
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syn >>= ARM_INSN_START_WORD2_SHIFT;
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/* We check and clear insn_start_idx to catch multiple updates. */
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assert(s->insn_start != NULL);
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tcg_set_insn_start_param(s->insn_start, 2, syn);
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s->insn_start = NULL;
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}
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static inline int curr_insn_len(DisasContext *s)
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{
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return s->base.pc_next - s->pc_curr;
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}
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/* is_jmp field values */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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/* CPU state was modified dynamically; exit to main loop for interrupts. */
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#define DISAS_UPDATE_EXIT DISAS_TARGET_1
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/* These instructions trap after executing, so the A32/T32 decoder must
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* defer them until after the conditional execution state has been updated.
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* WFI also needs special handling when single-stepping.
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*/
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#define DISAS_WFI DISAS_TARGET_2
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#define DISAS_SWI DISAS_TARGET_3
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/* WFE */
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#define DISAS_WFE DISAS_TARGET_4
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#define DISAS_HVC DISAS_TARGET_5
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#define DISAS_SMC DISAS_TARGET_6
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#define DISAS_YIELD DISAS_TARGET_7
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/* M profile branch which might be an exception return (and so needs
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* custom end-of-TB code)
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*/
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#define DISAS_BX_EXCRET DISAS_TARGET_8
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/*
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* For instructions which want an immediate exit to the main loop, as opposed
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* to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
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* doesn't write the PC on exiting the translation loop so you need to ensure
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* something (gen_a64_update_pc or runtime helper) has done so before we reach
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* return from cpu_tb_exec.
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*/
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#define DISAS_EXIT DISAS_TARGET_9
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/* CPU state was modified dynamically; no need to exit, but do not chain. */
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#define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
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#ifdef TARGET_AARCH64
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void a64_translate_init(void);
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void gen_a64_update_pc(DisasContext *s, target_long diff);
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extern const TranslatorOps aarch64_translator_ops;
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#else
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static inline void a64_translate_init(void)
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{
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}
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static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
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{
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}
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#endif
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void arm_test_cc(DisasCompare *cmp, int cc);
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void arm_free_cc(DisasCompare *cmp);
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void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
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void arm_gen_test_cc(int cc, TCGLabel *label);
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MemOp pow2_align(unsigned i);
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void unallocated_encoding(DisasContext *s);
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void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
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uint32_t syn, uint32_t target_el);
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void gen_exception_insn(DisasContext *s, target_long pc_diff,
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int excp, uint32_t syn);
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/* Return state of Alternate Half-precision flag, caller frees result */
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static inline TCGv_i32 get_ahp_flag(void)
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{
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TCGv_i32 ret = tcg_temp_new_i32();
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tcg_gen_ld_i32(ret, cpu_env,
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offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
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tcg_gen_extract_i32(ret, ret, 26, 1);
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return ret;
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}
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/* Set bits within PSTATE. */
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static inline void set_pstate_bits(uint32_t bits)
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{
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TCGv_i32 p = tcg_temp_new_i32();
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tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
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tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_gen_ori_i32(p, p, bits);
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tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_temp_free_i32(p);
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}
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/* Clear bits within PSTATE. */
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static inline void clear_pstate_bits(uint32_t bits)
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{
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TCGv_i32 p = tcg_temp_new_i32();
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tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
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tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_gen_andi_i32(p, p, ~bits);
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tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
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tcg_temp_free_i32(p);
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}
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/* If the singlestep state is Active-not-pending, advance to Active-pending. */
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static inline void gen_ss_advance(DisasContext *s)
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{
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if (s->ss_active) {
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s->pstate_ss = 0;
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clear_pstate_bits(PSTATE_SS);
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}
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}
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/* Generate an architectural singlestep exception */
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static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
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{
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/* Fill in the same_el field of the syndrome in the helper. */
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uint32_t syn = syn_swstep(false, isv, ex);
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gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn));
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}
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/*
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* Given a VFP floating point constant encoded into an 8 bit immediate in an
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* instruction, expand it to the actual constant value of the specified
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* size, as per the VFPExpandImm() pseudocode in the Arm ARM.
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*/
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uint64_t vfp_expand_imm(int size, uint8_t imm8);
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/* Vector operations shared between ARM and AArch64. */
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void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
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void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
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void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
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void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
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void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
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void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
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int64_t shift, uint32_t opr_sz, uint32_t max_sz);
|
|
void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
|
|
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
|
|
void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
|
|
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
|
|
void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
|
|
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
|
|
|
|
void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
|
|
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
|
|
void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
|
|
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
|
|
|
|
void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
|
|
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
|
|
void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
|
|
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
|
|
|
|
void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
|
|
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
|
|
void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
|
|
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
|
|
|
|
void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
|
|
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
|
|
void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
|
|
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
|
|
|
|
/*
|
|
* Forward to the isar_feature_* tests given a DisasContext pointer.
|
|
*/
|
|
#define dc_isar_feature(name, ctx) \
|
|
({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
|
|
|
|
/* Note that the gvec expanders operate on offsets + sizes. */
|
|
typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
|
|
typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
|
|
uint32_t, uint32_t);
|
|
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
|
|
uint32_t, uint32_t, uint32_t);
|
|
typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
|
|
uint32_t, uint32_t, uint32_t);
|
|
|
|
/* Function prototype for gen_ functions for calling Neon helpers */
|
|
typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
|
|
typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
|
|
typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
|
|
typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
|
|
typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
|
|
TCGv_i32, TCGv_i32);
|
|
typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
|
|
typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
|
|
typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
|
|
typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
|
|
typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
|
|
typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
|
|
typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
|
|
typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
|
|
typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
|
|
typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
|
|
typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
|
|
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
|
|
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
|
|
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
|
|
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
|
|
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
|
|
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
|
|
typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
|
|
|
|
/**
|
|
* arm_tbflags_from_tb:
|
|
* @tb: the TranslationBlock
|
|
*
|
|
* Extract the flag values from @tb.
|
|
*/
|
|
static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
|
|
{
|
|
return (CPUARMTBFlags){ tb->flags, tb->cs_base };
|
|
}
|
|
|
|
/*
|
|
* Enum for argument to fpstatus_ptr().
|
|
*/
|
|
typedef enum ARMFPStatusFlavour {
|
|
FPST_FPCR,
|
|
FPST_FPCR_F16,
|
|
FPST_STD,
|
|
FPST_STD_F16,
|
|
} ARMFPStatusFlavour;
|
|
|
|
/**
|
|
* fpstatus_ptr: return TCGv_ptr to the specified fp_status field
|
|
*
|
|
* We have multiple softfloat float_status fields in the Arm CPU state struct
|
|
* (see the comment in cpu.h for details). Return a TCGv_ptr which has
|
|
* been set up to point to the requested field in the CPU state struct.
|
|
* The options are:
|
|
*
|
|
* FPST_FPCR
|
|
* for non-FP16 operations controlled by the FPCR
|
|
* FPST_FPCR_F16
|
|
* for operations controlled by the FPCR where FPCR.FZ16 is to be used
|
|
* FPST_STD
|
|
* for A32/T32 Neon operations using the "standard FPSCR value"
|
|
* FPST_STD_F16
|
|
* as FPST_STD, but where FPCR.FZ16 is to be used
|
|
*/
|
|
static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
|
|
{
|
|
TCGv_ptr statusptr = tcg_temp_new_ptr();
|
|
int offset;
|
|
|
|
switch (flavour) {
|
|
case FPST_FPCR:
|
|
offset = offsetof(CPUARMState, vfp.fp_status);
|
|
break;
|
|
case FPST_FPCR_F16:
|
|
offset = offsetof(CPUARMState, vfp.fp_status_f16);
|
|
break;
|
|
case FPST_STD:
|
|
offset = offsetof(CPUARMState, vfp.standard_fp_status);
|
|
break;
|
|
case FPST_STD_F16:
|
|
offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
tcg_gen_addi_ptr(statusptr, cpu_env, offset);
|
|
return statusptr;
|
|
}
|
|
|
|
/**
|
|
* finalize_memop:
|
|
* @s: DisasContext
|
|
* @opc: size+sign+align of the memory operation
|
|
*
|
|
* Build the complete MemOp for a memory operation, including alignment
|
|
* and endianness.
|
|
*
|
|
* If (op & MO_AMASK) then the operation already contains the required
|
|
* alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally
|
|
* unaligned operation, e.g. for AccType_NORMAL.
|
|
*
|
|
* In the latter case, there are configuration bits that require alignment,
|
|
* and this is applied here. Note that there is no way to indicate that
|
|
* no alignment should ever be enforced; this must be handled manually.
|
|
*/
|
|
static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
|
|
{
|
|
if (s->align_mem && !(opc & MO_AMASK)) {
|
|
opc |= MO_ALIGN;
|
|
}
|
|
return opc | s->be_data;
|
|
}
|
|
|
|
/**
|
|
* asimd_imm_const: Expand an encoded SIMD constant value
|
|
*
|
|
* Expand a SIMD constant value. This is essentially the pseudocode
|
|
* AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
|
|
* VMVN and VBIC (when cmode < 14 && op == 1).
|
|
*
|
|
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
|
|
* callers must catch this; we return the 64-bit constant value defined
|
|
* for AArch64.
|
|
*
|
|
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
|
|
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
|
|
* we produce an immediate constant value of 0 in these cases.
|
|
*/
|
|
uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
|
|
|
|
/*
|
|
* gen_disas_label:
|
|
* Create a label and cache a copy of pc_save.
|
|
*/
|
|
static inline DisasLabel gen_disas_label(DisasContext *s)
|
|
{
|
|
return (DisasLabel){
|
|
.label = gen_new_label(),
|
|
.pc_save = s->pc_save,
|
|
};
|
|
}
|
|
|
|
/*
|
|
* set_disas_label:
|
|
* Emit a label and restore the cached copy of pc_save.
|
|
*/
|
|
static inline void set_disas_label(DisasContext *s, DisasLabel l)
|
|
{
|
|
gen_set_label(l.label);
|
|
s->pc_save = l.pc_save;
|
|
}
|
|
|
|
static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
|
|
{
|
|
TCGv_ptr ret = tcg_temp_new_ptr();
|
|
gen_helper_lookup_cp_reg(ret, cpu_env, tcg_constant_i32(key));
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Helpers for implementing sets of trans_* functions.
|
|
* Defer the implementation of NAME to FUNC, with optional extra arguments.
|
|
*/
|
|
#define TRANS(NAME, FUNC, ...) \
|
|
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
|
|
{ return FUNC(s, __VA_ARGS__); }
|
|
#define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
|
|
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
|
|
{ return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
|
|
|
|
#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \
|
|
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
|
|
{ \
|
|
s->is_nonstreaming = true; \
|
|
return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
|
|
}
|
|
|
|
#endif /* TARGET_ARM_TRANSLATE_H */
|