qemu-e2k/target
Yang Zhong 2605188240 target/i386: disable VMX features if nested=0
If kvm does not support VMX feature by nested=0, the kvm_vmx_basic
can't get the right value from MSR_IA32_VMX_BASIC register, which
make qemu coredump when qemu do KVM_SET_MSRS.

The coredump info:
error: failed to set MSR 0x480 to 0x0
kvm_put_msrs: Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed.

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20191206071111.12128-1-yang.zhong@intel.com>
Reported-by: Catherine Ho <catherine.hecx@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-06 12:35:40 +01:00
..
alpha target/alpha: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
arm target/arm: Honor HCR_EL2.TID3 trapping requirements 2019-11-26 13:55:37 +00:00
cris
hppa target/hppa: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
i386 target/i386: disable VMX features if nested=0 2019-12-06 12:35:40 +01:00
lm32
m68k target/m68k: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
microblaze target/microblaze: Plug temp leak around eval_cond_jmp() 2019-11-12 16:35:26 +01:00
mips
moxie
nios2
openrisc target/openrisc: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
ppc spapr/kvm: Set default cpu model for all machine classes 2019-11-18 11:50:39 +01:00
riscv target/riscv: Remove atomic accesses to MIP CSR 2019-11-14 09:53:28 -08:00
s390x
sh4
sparc target/sparc: Define an enumeration for accessing env->regwptr 2019-11-06 13:35:25 +01:00
tilegx
tricore
unicore32
xtensa target/xtensa: fetch code with translator_ld 2019-10-28 15:12:38 +00:00