bf7720024c
Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-8-f4bug@amsat.org>
28 lines
1.2 KiB
Plaintext
28 lines
1.2 KiB
Plaintext
# MIPS VR5432 instruction set extensions
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#
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# Copyright (C) 2021 Philippe Mathieu-Daudé
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#
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# SPDX-License-Identifier: LGPL-2.1-or-later
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#
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# Reference: VR5432 Microprocessor User’s Manual
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# (Document Number U13751EU5V0UM00)
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&r rs rt rd
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@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r
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MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd
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MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd
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MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd
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MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd
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MSAC 000000 ..... ..... ..... 00111011000 @rs_rt_rd
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MSACU 000000 ..... ..... ..... 00111011001 @rs_rt_rd
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MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd
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MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd
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MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd
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MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd
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MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd
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MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd
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MSACHI 000000 ..... ..... ..... 01111011000 @rs_rt_rd
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MSACHIU 000000 ..... ..... ..... 01111011001 @rs_rt_rd
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