Richard Henderson 6ecf39e2dd target/riscv: Use {get, dest}_gpr for integer load/store ... Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-09-01 11:59:12 +10:00
..
trans_privileged.c.inc	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
trans_rva.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvb.c.inc	target/riscv: Use DisasExtend in shift operations	2021-09-01 11:59:12 +10:00
trans_rvd.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvf.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvh.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvi.c.inc	target/riscv: Use {get, dest}_gpr for integer load/store	2021-09-01 11:59:12 +10:00
trans_rvm.c.inc	target/riscv: Move gen_* helpers for RVM	2021-09-01 11:59:12 +10:00
trans_rvv.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00